Takahiro Irita - researchr alias

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Viewing Publication 1 - 24 from 24

2022

A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D ControlKatsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei. jssc, 57(1):115-126, 2022. [doi]

2021

4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D ControlKatsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei. isscc 2021: 56-58 [doi]

2017

2016

2013

2010

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation CircuitsKenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori. jssc, 45(1):59-68, 2010. [doi]

2009

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMUMasayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama. jssc, 44(1):83-89, 2009. [doi]

A 342mW mobile application processor with full-HD multi-standard video codecKenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori. isscc 2009: 158-159 [doi]

A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory managementTatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka. aspdac 2009: 535-539 [doi]

2008

A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMUM. Naruse, Tatsuya Kamei, Toshihiro Hattori, Takahiro Irita, Kenichi Nitta, Takao Koike, Shinichi Yoshioka, Koji Ohno, M. Saigusa, M. Sakata, Y. Kodama, Y. Arai, T. Komuro. isscc 2008: 260-261 [doi]

2007

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOSMasayuki Ito, Toshihiro Hattori, Takahiro Irita, Ken Tatezawa, Fumihito Tanaka, Kenji Hirose, Shinichi Yoshioka, Koji Ohno, Reiko Tsuchihashi, Minoru Sakata, Masayuki Yamamoto, Yuji Aral. isscc 2007: 274-602 [doi]

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCsYusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie. jssc, 42(1):74-83, 2007. [doi]

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time ResolutionYusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno. jssc, 42(4):784-789, 2007. [doi]

A Hardware Accelerator for Java:::TM::: Platforms on a 130-nm Embedded Processor CoreTetsuya Yamada, Naohiko Irie, Takanobu Tsunoda, Takahiro Irita, Kenji Kitagawa, Ryohei Yoshida, Keisuke Toyama, Motoaki Satoyama. ieicet, 90-C(2):523-530, 2007. [doi]

2006

SH-MobileG1: A single-chip application and dual-mode baseband processorMasayuki Ito, Takahiro Irita, Eiji Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, Hiroshi Yagi, Saneaki Tamaki, Ken Tatezawa, Toshihiro Hattori, Shinichi Yoshioka, Koji Ohno. hotchips 2006: 1-24 [doi]

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU ProcessorYusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, T. Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, N. Irie. isscc 2006: 2200-2209 [doi]

2005

SH-mobile - low power application processor for cellular [3G cellular phones]S. Kamae, Takahiro Irita, A. Tsukimori, S. Tarnaki, Toshihiro Hattori, Shinichi Yoshioka. iscas 2005: 5349-5352 [doi]

1999

Microprocessor architecture utilizing redundant-binary operationTakahiro Irita, Takayuki Ogura, Minoru Fujishima, Koichiro Hoh. scjapan, 30(13):106-115, 1999. [doi]

1998

Generation of chaos with simple sets of semiconductor devicesKoichiro Hoh, Takahiro Irita, Teppei Tsujita, Minoru Fujishima. kes 1998: 250-259 [doi]

Self-oscillating chaos generator using CMOS multivibratorTeppei Tsujita, Takahiro Irita, Minoru Fujishima, Koichiro Hoh. kes 1998: 213-217 [doi]

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