Tomasz S. Czajkowski - researchr alias

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Viewing Publication 1 - 20 from 20

2023

Efficient Data Streaming for a Tightly-Coupled Coarse-Grained Reconfigurable ArrayMahdi Abbaszadeh, Tarek S. Abdelrahman, Reza Azimi, Tomasz S. Czajkowski, Maziar Goudarzi. ipps 2023: 435-443 [doi]

2018

2015

Silicon Verification using High-Level Design Tools (Abstract Only)Tomasz S. Czajkowski. fpga 2015: 272 [doi]

High-Level Design Tools for Floating Point FPGAsDeshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski. fpga 2015: 9-12 [doi]

2014

Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level SynthesisBlair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu-Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson. euc 2014: 120-129 [doi]

2013

2012

2011

LegUp: high-level synthesis for FPGA-based processor/accelerator systemsAndrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski. fpga 2011: 33-36 [doi]

2010

Decomposition-Based Vectorless Toggle Rate Computation for FPGA CircuitsTomasz S. Czajkowski, Stephen Dean Brown. tcad, 29(11):1723-1735, 2010. [doi]

2008

Functionally linear decomposition and synthesis of logic circuits for FPGAsTomasz S. Czajkowski, Stephen Dean Brown. dac 2008: 18-23 [doi]

Fast toggle rate computation for FPGA circuitsTomasz S. Czajkowski, Stephen Dean Brown. fpl 2008: 65-70 [doi]

Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAsTomasz S. Czajkowski, Stephen Dean Brown. tcad, 27(12):2236-2249, 2008. [doi]

2007

Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA CircuitsTomasz S. Czajkowski, Stephen Dean Brown. dac 2007: 324-329 [doi]

2004

A synthesis oriented omniscient manual editorTomasz S. Czajkowski, Jonathan Rose. fpga 2004: 89-98 [doi]

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