Abstract is missing.
- At the core of system scalingGreg Yeric. 1-2 [doi]
- Ultra-low energy systems: Analog to informationAhmad Bahai. 3-6 [doi]
- Neuromorophic vision sensing and processingTobi Delbrück. 7-14 [doi]
- Polymer Microwave Fibers: A blend of RF, copper and optical communicationPatrick Reynaert, Maarten Tytgat, Wouter Volkaerts, Alexander Standaert, Yang Zhang, Maxime De Wit, Niels Van Thienen. 15-20 [doi]
- 5G and the future of IoTGerhard P. Fettweis. 21-24 [doi]
- IoT: The era of LPWAN is starting nowJean-Paul Bardyn, Thierry Melly, Olivier Seller, Nicolas Sornin. 25-30 [doi]
- WSN for Machine Area Network applicationsXiaolin Lu, Il-Han Kim, Ariton E. Xhafa, Jianwei Zhou. 31-36 [doi]
- ®-A53 using static biasing-anticipationFady Abouzeid, Christophe Bernicot, Sylvain Clerc, Jean-Marc Daveau, Gilles Gasiot, Daniel Noblet, Dimitri Soussan, Philippe Roche. 37-40 [doi]
- Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operationMarc Pons, Thanh-Chau Le, Claude Arm, Daniel Séverac, Jean-Luc Nagel, Marc-Nicolas Morgan, Stephane Emery. 41-44 [doi]
- A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logicHarsh N. Patel, Abhishek Roy, Farah B. Yahya, Ningxi Liu, Benton H. Calhoun, Kazuyuki Kumeno, Makoto Yasuda, Akihiko Harada, Taiji Ema. 45-48 [doi]
- Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approachGirish Pahwa, Tapas Dutta, Amit Agarwal, Yogesh Singh Chauhan. 49-54 [doi]
- Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspectiveTarun Agarwal, Iuliana Radu, Praveen Raghavan, Gianluca Fiori, Aaron Thean, Marc M. Heyns, Wim Dehaene. 55-58 [doi]
- Experimental demonstration of a nanoelectromechanical switch-based logic library including sequential and combinational gatesChristopher Lawrence Ayala, Antonios Bazigos, Daniel Grogg, Ute Drechsler, Christoph Hagleitner. 59-62 [doi]
- Reflection amplifier based on graphenePankaj Sharma, Laurent Syavoch Bernard, Antonios Bazigos, Arnaud Magrez, Laszlo Forro, Adrian M. Ionescu. 63-66 [doi]
- Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash processMasahiro Tanaka, Kota Tsurumi, Tomoya Ishii, Ken Takeuchi. 67-70 [doi]
- A highly tunable 65-nm CMOS LIF neuron for a large scale neuromorphic systemSyed Ahmed Aamir, Paul Müller 0002, Andreas Hartel, Johannes Schemmel, Karlheinz Meier. 71-74 [doi]
- Delay partitioning helps reducing variability in 3DVLSIA. Ayres, Olivier Rozeau, B. Borot, Laurent Fesquet, Maud Vinet. 75-78 [doi]
- 20.3dB 0.39mW AM detector with single-transistor active inductor in bendable a-IGZO TFTTilo Meister, Koichi Ishida, Reza Shabanpour, Bahman Kheradmand Boroujeni, Corrado Carta, Niko Munzenrieder, Luisa Petti, Giuseppe Cantarella, Giovanni A. Salvatore, Gerhard Tröster, Frank Ellinger. 79-82 [doi]
- History, present state-of-art and future of incremental ADCsChia-Hung Chen, Yi Zhang, Gabor C. Temes. 83-86 [doi]
- A wearable ECG monitoring device with flexible embedded denoising and compressionChenyu Wang, Han Jin, Yajie Qin, Li-Rong Zheng. 87-90 [doi]
- A 9.8b-ENOB 5.5fJ/step fully-passive compressive sensing SAR ADC for WSN applicationsWenjuan Guo, Nan Sun. 91-94 [doi]
- Energy performance of nonvolatile power-gating SRAM using SOTB technologyYusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara. 95-98 [doi]
- Development of high sensitivity CMOS-MEMS inertia sensor and its application to early-stage diagnosis of Parkinson's diseaseKazuya Masu, Daisuke Yamane, Katsuyuki Machida, Masato Sone, Yoshihiro Miyake. 99-104 [doi]
- Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfacesTetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura. 105-108 [doi]
- 2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applicationsChi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Hue-Min Lin, Chun-Chia Chen, Min-Hao Chiu, Ping Chao, Ming-Long Wu, Meng-Jye Hu, Sheng-Jen Wang, Che-Hong Chen, Shun-Hsiang Chuang, Hsiu-Yi Lin, Fu-Chun Yeh, Chia Hung Kao, Yi-Chang Chen, Chia-Lin Ho, Yenchieh Huang, Hsiao-En Chen, Chih-Wen Yang, Hsuan-Wen Peng. 109-112 [doi]
- An energy-scalable accelerator for blind image deblurringPriyanka Raina, Mehul Tikekar, Anantha P. Chandrakasan. 113-116 [doi]
- An 8.3mW 1.6Msamples/s multi-modal event-driven speech enhancement processor for robust speech recognition in smart glassesJinmook Lee, Seongwook Park, Injoon Hong, Hoi-Jun Yoo. 117-120 [doi]
- An 802.11a/b/g/n/ac WLAN Transceiver for 2×2 MIMO and simultaneous dual-band operation with +29 dBm Psat integrated power amplifiersShing Tak Yan, Lu Ye, Hongbing Wu, Raghavendra Kulkarni, Edward Myers, Hsieh-Chih Shih, Shadi Saberi, Darshan Kadia, Dizle Ozis, Lei Zhou, Eric Middleton, Joo Leong Tham. 121-124 [doi]
- A 0.9-1.2V supplied, 2.4GHz Bluetooth Low Energy 4.0/4.2 and 802.15.4 transceiver SoC optimized for battery lifeXiaoyan Wang, Johan H. C. van den Heuvel, Gert-Jan van Schaik, Chuang Lu, Yuming He, Ao Ba, Benjamin Busze, Ming Ding, Yao-Hong Liu, Nick Winkel, Menno Wildeboer, Christian Bachmann, Kathleen Philips. 125-128 [doi]
- A 51.4 Mb/s FSK transmitter employing a Phase Domain Digital Synthesizer with 1.5 µs start-up for energy efficient duty cyclingRaghavasimhan Thirunarayanan, David Ruffieux, Nicola Scolari, Christian C. Enz. 129-132 [doi]
- An energy harvested ultra-low power transceiver for Internet of Medical ThingsYashar Rajavi, Mazhareddin Taghivand, Kamal Aggarwal, Andrew Ma, Ada S. Y. Poon. 133-136 [doi]
- A 433 MHz 54 µW OOK/FSK/PSK compatible wake-up receiver with 11 µW low-power mode based on injection-locked oscillatorShih-En Chen, Kuang-Wei Cheng. 137-140 [doi]
- A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverterTakuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata. 141-144 [doi]
- A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOIIlias Sourikopoulos, Antoine Frappe, Andreia Cathelin, Laurent Clavier, Andreas Kaiser. 145-148 [doi]
- A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stabilityHiroki Asano, Tetsuya Hirose, Keishi Tsubaki, T. Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa. 149-152 [doi]
- A ΣΔ sense chain using chopped integrators for ultra-low-noise MEMS systemChristian Fraisse, Angelo Nagari. 153-156 [doi]
- A 82nW chaotic-map true random number generator based on sub-ranging SAR ADCMinseo Kim, Unsoo Ha, Yongsu Lee, Kyuho Jason Lee, Hoi-Jun Yoo. 157-160 [doi]
- Data converter reflections: 19 papers from the last ten years that deserve a second lookDavid Robertson, Aaron Buchwald, Michael Flynn, Hae-Seung Lee, Un-Ku Moon, Boris Murmann. 161-164 [doi]
- 2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBBAshish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik. 165-168 [doi]
- 2 pipelined-SAR ADC with merged-residue DAC for noise reductionJianyu Zhong, Yan Zhu 0001, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. 169-172 [doi]
- 2 column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminatorSaikrishna Ganta, Alfredo Tomasini, Ajay Taparia, Taehee Cho, Mandar Kulkarni, Ozan Erdogan. 173-176 [doi]
- A compiled 3.5fJ/conv.step 9b 20MS/s SAR ADC for wireless applications in 28nm FDSOICarsten Wulff, Trond Ytterdal. 177-180 [doi]
- A 65nm CMOS wideband TDD front-end with integrated T/R switching via PA re-useXiao Xiao, Amanda Pratt, Ali M. Niknejad, Elad Alon, Borivoje Nikolic. 181-184 [doi]
- A tunable gain and tunable band active balun LNA for IEEE 802.11ac WLAN receiversSuchendranath Popuri, Vijaya Sankara Rao Pasupureddi, Johannes Sturm. 185-188 [doi]
- A recursive house-of-cards digital power amplifier employing a λ/4-less Doherty power combiner in 65nm CMOSLoai G. Salem, James F. Buckwalter, Patrick P. Mercier. 189-192 [doi]
- A 200-225 GHz SiGe Power Amplifier with peak Psat of 9.6 dBm using wideband power combinationNeelanjan Sarmah, Klaus Aufinger, Rudolf Lachner, Ullrich R. Pfeiffer. 193-196 [doi]
- An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dBDongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa. 197-200 [doi]
- A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOSWerner Grollitsch, Roberto Nonis. 201-204 [doi]
- A 2 GHz 3.1 mW type-I digital ring-based PLLZule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. 205-208 [doi]
- A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noiseYing Wu, Mina Shahmohammadi, Yue Chen, Ping Lu, Robert Bogdan Staszewski. 209-212 [doi]
- Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOSCheng-Ru Ho, Mike Shuo-Wei Chen. 213-216 [doi]
- An array of fully-integrated quadrature TX/RX NMR field probes for MRI trajectory mappingJonas Handwerker, M. Eder, M. Tibiletti, V. Rasche, K. Scheffler, Joachim Becker, Maurits Ortmanns, Jens Anders. 217-220 [doi]
- A column-and-row-parallel CMOS image sensor with thermal and 1/f noise suppression techniquesHa Le-Thai, Adi Xhakoni, Georges G. E. Gielen. 221-224 [doi]
- An impedance-tracking battery-less arbitrary-waveform neurostimulator with load-adaptive 20V voltage complianceHossein Kassiri, Gairik Dutta, Nima Soltani, Chang Liu, Yu Hu, Roman Genov. 225-228 [doi]
- A high-voltage compliant, electrode-invariant neural stimulator front-end in 65nm bulk-CMOSEric Pepin, John Uehlin, Daniel Micheletti, Steve I. Perlmutter, Jacques C. Rudell. 229-232 [doi]
- Stimulation artifact rejection in closed-loop, distributed neural interfacesErik J. Peterson, David A. Dinsmoor, Dustin J. Tyler, Timothy J. Denison. 233-236 [doi]
- A 0.3 V, 49 fJ/conv.-step VCO-based delta sigma modulator with self-compensated current reference for variation toleranceNeelakantan Narasimman, Tony T. Kim. 237-240 [doi]
- A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOSShaolan Li, Nan Sun. 241-244 [doi]
- A multi-mode SC audio ΣΔ Modulator for MEMS microphones with reconfigurable power consumption, noise-shaping order, and DRMarco Grassi, Fabrizio Conso, G. Rocca, Piero Malcovati, Andrea Baschirotto. 245-248 [doi]
- A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adderZhijie Chen, Masaya Miyahara, Akira Matsuzawa. 249-252 [doi]
- A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filterTohru Kaneko, Yuya Kimura, Koji Hirose, Masaya Miyahara, Akira Matsuzawa. 253-256 [doi]
- A 16.07pJ/cycle 31MHz fully differential transmission gate logic ARM Cortex M0 core in 40nm CMOSHans Reyserhove, Wim Dehaene. 257-260 [doi]
- DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustmentJeremy Constantin, Andrea Bonetti, Adam Teman, Christoph Muller, Lorenz Schmid, Andreas Burg. 261-264 [doi]
- FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUsKan Takeuchi, Masaki Shimada, Takeshi Okagaki, Koji Shibutani, Koji Nii, Fumio Tsuchiya. 265-268 [doi]
- Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoCBen Keller, Martin Cochet, Brian Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, Alberto Puggelli, Stevo Bailey, Pi-Feng Chiu, Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic. 269-272 [doi]
- A 40nm bulk CMOS line driver for broadband communicationJan Cools, Patrick Reynaert. 273-276 [doi]
- A 650 V, 3 A three-phase fully-integrated BLDC motor driver with charge pump and level shiftersValentijn De Smedt, Jef Thone, Mike Wens. 277-280 [doi]
- High-voltage tolerant bi-state self-biasing output driver using cascade complementary latches in twin-well CMOS technologyR. J. E. Jansen, S. Lindner. 281-284 [doi]
- A Differential Difference Amplifier with Dynamic Resistive Degeneration for MEMS microphonesAndrea Barbieri, Sergio Pernici. 285-288 [doi]
- th-Order FLFB analog filterAlessandra Pipino, Marcello De Matteis, Alessandro Pezzotta, Federica Resta, Stefano D'Amico, Andrea Baschirotto. 289-292 [doi]
- A 12-Gb/s dual-channel transceiver for CMOS image sensor systemsSang-Hoon Kim, Hoon Shin, Youngkyun Jeong, June-Hee Lee, Jaehyuk Choi, Jung-Hoon Chun. 293-296 [doi]
- A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFETMarc Erett, James Hudner, Declan Carey, Ronan Casey, Kevin Geary, Kay Hearne, Pedro Neto, Thomas Mallard, Vikas Sooden, Mark Smyth, Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang. 297-300 [doi]
- A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency trackingTetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada. 301-304 [doi]
- A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOSXuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang. 305-308 [doi]
- A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOSHazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl. 309-312 [doi]
- A ZVS resonant receiver with maximum efficiency tracking for device-to-device wireless chargingNachiket V. Desai, Anantha P. Chandrakasan. 313-316 [doi]
- A 130nm hybrid low dropout regulator based on switched mode control for digital load circuitsSaad Bin Nasir, Shreyas Sen, Arijit Raychowdhury. 317-320 [doi]
- UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reductionSamantak Gangopadhyay, Saad Bin Nasir, A. Subramanian, Visvesh Sathe, Arijit Raychowdhury. 321-324 [doi]
- Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dipAlexis Schindler, Benno Koeppl, Ansgar Pottbaecker, Markus Zannoth, Bernhard Wicht. 325-328 [doi]
- Bang-bang digital PLLsSalvatore Levantino. 329-334 [doi]
- A 0.2-11.7GHz, high accuracy injection-locking multi-phase generation with mixed analog/digital calibration loops in 28nm FDSOI CMOSG. Anzalone, Enrico Monaco, G. Albasini, Simone Erba, Andrea Mazzanti. 335-338 [doi]
- 2 600µW 32kHz input 307MHz output PLL with 190psrms jitter in 28nm FD-SOIAbhirup Lahiri, Nitin Gupta. 339-342 [doi]
- A 80 nW, 32 kHz charge-pump based ultra low power oscillator with temperature compensationMarkus Scholl, Ye Zhang 0003, Ralf Wunderlich, Stefan Heinen. 343-346 [doi]
- A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurementWei-Zen Chen, Po-I. Kuo. 347-350 [doi]
- Self-aligned open-loop local quadrature phase generatorMichael Kalcher, Daniel Gruber, Davide Ponton. 351-354 [doi]
- A 1GHz signal bandwidth 4-channel-I/Q polyphase-FFT filter bankHundo Shin, Ramesh Harjani. 355-358 [doi]
- An easily extendable FFT based four-channel, four-beam receiver with progressive partial spatial filtering in 65nmQingrui Meng, Ramesh Harjani. 359-362 [doi]
- A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceiversFabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua. 363-366 [doi]
- Design of broadband mm-wave and THz frequency doublersHamidreza Aghasi, Ehsan Afshari. 367-372 [doi]
- A multi-core VCO and a frequency quadrupler for E-Band adaptive-modulation links in 55nm BiCMOSLorenzo Iotti, Andrea Mazzanti, Francesco Svelto. 373-376 [doi]
- A 1∼1.5 GHz capacitive coupled inductor-less multi-ring oscillator with improved phase noiseRuixin Wang, Fa Foster Dai. 377-380 [doi]
- An 85-GHz fully integrated all digital fractional frequency synthesizer for e-band backhaul and radar applications in 55-nm BiCMOSM. Houdebine, Emmanuel Chataigner, R. Boulestin, C. Grundrich, D. Thevenet, S. Pruvost, H. Sherry, F. Colmagro, F. Bailleul, Sébastien Dedieu. 381-384 [doi]
- A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOSArindam Sanyal, Nan Sun. 385-388 [doi]
- An energy-efficient 17-bit noise-shaping Dual-Slope Capacitance-to-Digital Converter for MEMS sensorsJ. P. Sanjurjo, E. Prefasi, C. Buffa, R. Gaggl. 389-392 [doi]
- A 2 MS/s 10A Hall current sensor SoC with digital compressive sensing encoder in 0.16 µm BCDMarco Crescentini, M. Biondi, Marco Bennati, P. Alberti, G. Luciani, C. Tamburini, Matteo Pizzotti, Aldo Romani, Marco Tartagni, David E. Bellasi, Davide Rossi, Luca Benini, M. Marchesi, D. Cristaudo, Roberto Canegallo. 393-396 [doi]
- A hybrid multi-path CMOS magnetic sensor with 76 ppm/°C sensitivity driftJunfeng Jiang, Kofi A. A. Makinwa. 397-400 [doi]
- A high-gain, low-noise switched capacitor readout for FET-based THz detectorsMuhammad Ali, Matteo Perenzoni, David Stoppa. 401-404 [doi]
- A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integratorWenjuan Guo, Nan Sun. 405-408 [doi]
- A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-resetMaoqiang Liu, Arthur H. M. van Roermund, Pieter Harpe. 409-412 [doi]
- A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOSXiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun. 413-416 [doi]
- A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOSKareem Ragab, Nan Sun. 417-420 [doi]
- An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technologyDante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U. Fat Chio, Sai-Weng Sin, Rui Paulo Martins. 421-424 [doi]
- Register file circuits and post-deployment framework to monitor aging effects in fieldTeng Yang, Peter R. Kinget, Mingoo Seok. 425-428 [doi]
- A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOIBabak Mohammadi, Oskar Andersson, Joseph Nguyen, Lorenzo Ciampolini, Andreia Cathelin, Joachim Neves Rodrigues. 429-432 [doi]
- A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOIAvishek Biswas, Anantha P. Chandrakasan. 433-436 [doi]
- An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOIZhao Chuan Lee, M. Sultan M. Siddiqui, Zhi-Hui Kong, Tony Tae-Hyoung Kim. 437-440 [doi]
- A digitally-controlled 2-/3-phase 6-ratio switched- capacitor DC-DC converter with adaptive ripple reduction and efficiency improvementsJunmin Jiang, Yan Lu, Wing-Hung Ki. 441-444 [doi]
- MIMO Switched-Capacitor converter using only parasitic capacitance with Scalable Parasitic Charge RedistributionNicolas Butzen, Michiel Steyaert. 445-448 [doi]
- A 120/230 Vrms-to-3.3V micro power supply with a fully integrated 17V SC DCDC converterDaniel Lutz, Peter Renz, Bernhard Wicht. 449-452 [doi]
- An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOSMonodeep Kar, Arvind Singh, Anand Rajan, Vivek De, Saibal Mukhopadhyay. 453-456 [doi]
- 0.89 mW on-chip jitter-measurement circuit for high speed clock with sub-picosecond resolutionEnkhbayasgalan Gantsog, Deyu Liu, Alyssa B. Apsel. 457-460 [doi]
- A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technologyKwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee. 461-464 [doi]
- Approximate 32-bit floating-point unit design with 53% power-area product reductionVincent Camus, Jeremy Schlachter, Christian Enz, Michael Gautschi, Frank K. Gürkaynak. 465-468 [doi]
- 2 inductive-coupling side-by-side chip linkSo Hasegawa, Junichiro Kadomoto, Atsutake Kosuge, Tadahiro Kuroda. 469-472 [doi]
- Supply boosting for high-performance processors in flip-chip packagesNathaniel Ross Pinckney, Dennis Sylvester, David Blaauw. 473-476 [doi]
- Design considerations for 50G+ backplane linksThomas Toifl, Matthias Braendli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Ilter Özkaya, Hazar Yueksel. 477-482 [doi]
- An 18Gbps polymer microwave fiber (PMF) communication link in 40nm CMOSNiels Van Thienen, Yang Zhang, Maxime De Wit, Patrick Reynaert. 483-486 [doi]
- A wideband monolithically integrated photonic receiver in 0.25-µm SiGe: C BiCMOS technologyM. H. Eissa, Ahmed Awny, G. Winzer, M. Kroh, Stefan Lischke, D. Knoll, Lars Zimmermann, Dietmar Kissinger, Ahmet Cagri Ulusoy. 487-490 [doi]
- A 12Gb/s, 8.6µApp input sensitivity, monolithic-integrated fully differential optical receiver in CMOS 45nm SOI processNandish Mehta, Chen Sun, Mark Wade, Sen Lin, Milos Popovic, Vladimir Stojanovic. 491-494 [doi]
- Phase and frequency self-configurable efficient low voltage harvester for zero power wearable devicesMilad Ataei, Alexis Boegli, Pierre-André Farine. 495-498 [doi]
- Time slot optimization algorithm for multisource energy harvesting systemsSung-Youb Jung, Myeong-Jae Park, Minbok Lee, Joonseok Yang, Jaeha Kim. 499-502 [doi]
- A time-based self-adaptive energy-harvesting MPPT with 5.1-µW power consumption and a wide tracking range of 10-µA to 1-mAKarim Rawy, Felix Kalathiparambil George, Dominic Maurath, Tony T. Kim. 503-506 [doi]
- 2 power generation and regulated multi-domain power delivery for self-powered imagingKhondker Zakir Ahmed, Mohammad Faisal Amir, Jong Hwan Ko, Saibal Mukhopadhyay. 507-510 [doi]