Table of Contents

• Twiddle factor transformation for pipelined FFT processingIn-Cheol Park, WonHee Son, Ji-Hoon Kim. 1-6 [doi]
• Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform EngineHani Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.. 7-12 [doi]
• Speed-area optimized FPGA implementation for Full Search Block MatchingSantosh Ghosh, Avishek Saha. 13-18 [doi]
• Bounded model checking of embedded software in wireless cognitive radio systemsNannan He, Michael S. Hsiao. 19-24 [doi]
• Application of symbolic computer algebra to arithmetic circuit verificationYuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi. 25-32 [doi]
• Continual hashing for efficient fine-grain state inconsistency detectionJae W. Lee, Myron King, Krste Asanovic. 33-40 [doi]
• Automatic SystemC TLM generation for custom communication platformsLochi Lo Chi Yu Lo, Samar Abdi. 41-46 [doi]
• Improving cache efficiency via resizing + remappingSubramanian Ramaswamy, Sudhakar Yalamanchili. 47-54 [doi]
• Exploring DRAM cache architectures for CMP server platformsLi Zhao, Ravi R. Iyer, Ramesh Illikkal, Donald Newell. 55-62 [doi]
• A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOSAmit Kumar 0002, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha. 63-70 [doi]
• Analytical thermal placement for VLSI lifetime improvement and minimum performance variationAndrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu. 71-77 [doi]
• Voltage drop reduction for on-chip power delivery considering leakage current variationsJeffrey Fan, Ning Mi, Sheldon X.-D. Tan. 78-83 [doi]
• On modeling impact of sub-wavelength lithography on transistorsAswin Sreedhar, Sandip Kundu. 84-90 [doi]
• Why we need statistical static timing analysisCristiano Forzan, Davide Pandini. 91-96 [doi]
• Statistical timing analysis using Kernel smoothingJennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak. 97-102 [doi]
• Tutorial: Software-defined radio technologyMark Cummings, Todor Cooklev. 103-104 [doi]
• A position-insensitive finished store bufferErika Gunadi, Mikko H. Lipasti. 105-112 [doi]
• A low overhead hardware technique for software integrity and confidentialityAustin Rogers, Milena Milenkovic, Aleksandar Milenkovic. 113-120 [doi]
• Cluster-level simultaneous multithreading for VLIW processorsManoj Gupta, Fermín Sánchez, Josep Llosa. 121-128 [doi]
• Evaluating voltage islands in CMPs under process variationsAbhishek Das, Serkan Ozdemir, Gokhan Memik, Alok N. Choudhary. 129-136 [doi]
• Non-arithmetic carry chains for reconfigurable fabricsMichael T. Frederick, Arun K. Somani. 137-143 [doi]
• FPGA global routing architecture optimization using a multicommodity flow approachYuanfang Hu, Yi Zhu, Michael Bedford Taylor, Chung-Kuan Cheng. 144-151 [doi]
• FPGA routing architecture analysis under variationsSuresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan. 152-157 [doi]
• Energy-aware co-processor selection for embedded processors on FPGAsAmir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee. 158-163 [doi]
• Benchmarks and performance analysis of decimal floating-point applicationsLiang-Kai Wang, Charles Tsen, Michael J. Schulte, Divya Jhalani. 164-170 [doi]
• Multi-core data streaming architecture for ray tracingYoshiyuki Kaeriyama, Daichi Zaitsu, Ken-ichi Suzuki, Hiroaki Kobayashi, Nobuyuki Ohba. 171-178 [doi]
• Hardware libraries: An architecture for economic acceleration in soft multi-core environmentsDavid Meisner, Sherief Reda. 179-186 [doi]
• Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processorsHai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi. 187-193 [doi]
• Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuitsLili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi. 194-201 [doi]
• Amdahl s figure of merit, SiGe HBT BiCMOS, and 3D chip stackingPhil Jacobs, Aamir Zia, Okan Erdogan, Paul M. Belemjian, Peng Jin, Jin-Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald. 202-207 [doi]
• Scan chain design for three-dimensional integrated circuits (3D ICs)Xiaoxia Wu, Paul Falkenstern, Yuan Xie. 208-214 [doi]
• The challenge in testing MIMO in a Wi-Fi or WiMAX contextKarsten Vandrup. 215 [doi]
• Challenges and prospects of SDR for mobile phonesUlrich Ramacher. 215 [doi]
• Exploring the interplay of yield, area, and performance in processor cachesHyunjin Lee, Sangyeun Cho, Bruce R. Childers. 216-223 [doi]
• Improving the reliability of on-chip L2 cache using redundancyKoustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan. 224-229 [doi]
• Reducing leakage power in peripheral circuits of L2 cachesHouman Homayoun, Alexander V. Veidenbaum. 230-237 [doi]
• Two-level ata prefetchingFei Gao, Hanyu Cui, Suleyman Sair. 238-244 [doi]
• Cache replacement based on reuse-distance predictionGeorgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras. 245-250 [doi]
• Constraint satisfaction in incremental placement with application to performance optimization under power constraintsHuan Ren, Shantanu Dutt. 251-258 [doi]
• Fine grain 3D integration for microarchitecture design through cube packing explorationYongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong. 259-266 [doi]
• Whitespace redistribution for thermal via insertion in 3D stacked ICsEric Wong, Sung Kyu Lim. 267-272 [doi]
• Placement and routing of RF embedded passive designs in LCP substrateMohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim. 273-279 [doi]
• A radix-10 SRT divider based on alternative BCD codingsÁlvaro Vázquez, Elisardo Antelo, Paolo Montuschi. 280-287 [doi]
• Hardware design of a Binary Integer Decimal-based floating-point adderCharles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte. 288-295 [doi]
• A parallel IEEE P754 decimal floating-point multiplierBrian J. Hickmann, Andrew Krioukov, Michael J. Schulte, Mark A. Erle. 296-303 [doi]
• Floating-point division algorithms for an x86 microprocessor with a rectangular multiplierMichael J. Schulte, Dimitri Tan, Carl Lemonds. 304-310 [doi]
• Optimized design of a double-precision floating-point multiply-add-dused unit for data dependenceGongqiong Li, Zhaolin Li. 311-316 [doi]
• Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessorSule Ozev, Daniel J. Sorin, Mahmut Yilmaz. 317-324 [doi]
• Improving the reliability of on-chip data caches under process variationsWei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu. 325-332 [doi]
• Prioritizing verification via value-based correctness criticalityJoonhyuk Yoo, Manoj Franklin. 333-340 [doi]
• Memory based computation using embedded cache for processor yield and reliability improvementSomnath Paul, Swarup Bhunia. 341-346 [doi]
• Accurate modeling and fault simulation of Byzantine resistive bridgesHugo Cheung, Sandeep K. Gupta. 347-353 [doi]
• Negative-skewed shadow registers for at-speed delay variation characterizationJie Li, John Lach. 354-359 [doi]
• An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnectsJianxun Liu, Wen-Ben Jone. 360-367 [doi]
• Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputsSiavash Bayat Sarmadi, M. Anwar Hasan. 368-375 [doi]
• Modeling soft error effects considering process variationsChong Zhao, Sujit Dey. 376-381 [doi]
• An automated runtime power-gating schemeMototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki. 382-387 [doi]
• A power gating scheme for ground bounce reduction during mode transitionKu He, Rong Luo, Yu Wang. 388-394 [doi]
• Dynamically compressible context architecture for low power coarse-grained reconfigurable arrayYoonjin Kim, Rabi N. Mahapatra. 395-400 [doi]
• Post-layout comparison of high performance 64b static adders in energy-delay spaceSheng Sun, Carl Sechen. 401-408 [doi]
• CAP: Criticality analysis for power-efficient speculative multithreadingJames Tuck, Wei Liu, Josep Torrellas. 409-416 [doi]
• Power-aware mapping for reconfigurable NoC architecturesMehdi Modarressi, Hamid Sarbazi-Azad. 417-422 [doi]
• LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translationJugash Chandarlapati, Mainak Chaudhuri. 423-430 [doi]
• Power efficient register file update approach for embedded processorsRaid Ayoub, Alex Orailoglu. 431-437 [doi]
• A technique for selecting CMOS transistor ordersTing Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen. 438-443 [doi]
• Algorithms to simplify multi-clock/edge timing constraintsVeerapaneni Nagbhushan, C. Y. Roger Chen. 444-449 [doi]
• An efficient gate delay model for VLSI designTing Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen. 450-455 [doi]
• Fast power network analysis with multiple clock domainsWanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng. 456-463 [doi]
• Statistical simulation of chip multiprocessors running multi-program workloadsDavy Genbrugge, Lieven Eeckhout. 464-471 [doi]
• Combining cluster sampling with single pass methods for efficient sampling regimen designPaul D. Bryan, Thomas M. Conte. 472-479 [doi]
• A novel O(1) parallel deadlock detection algorithm and architecture for multi-unit resource systemsXiang Xiao, Jaehwan John Lee. 480-487 [doi]
• Limits on voltage scaling for caches utilizing fault tolerant techniquesMohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi. 488-495 [doi]
• VOSCH: Voltage scaled cache hierarchiesWeng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li. 496-503 [doi]
• Exploiting eDRAM bandwidth with data prefetching: simulation and measurementsValentina Salapura, José R. Brunheroto, Fernando F. Redigolo, Alan Gara. 504-511 [doi]
• Digital calibration of RF transceivers for I-Q imbalances and nonlinearityErkan Acar, Sule Ozev. 512-517 [doi]
• Fault-based alternate test of RF componentsSelim Sermet Akbay, Abhijit Chatterjee. 518-525 [doi]
• Circuit-level mismatch modelling and yield optimization for CMOS analog circuitsMingjing Chen, Alex Orailoglu. 526-532 [doi]
• A Study on self-timed asynchronous subthreshold logicNiklas Lotze, Maurits Ortmanns, Yiannos Manoli. 533-540 [doi]
• SCAFFI: An intrachip FPGA asynchronous interface based on hard macrosJulian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans. 541-546 [doi]
• Passive compensation for high performance inter-chip communicationChun-Chen Liu, Haikun Zhu, Chung-Kuan Cheng. 547-552 [doi]
• Transparent mode flip-flops for collapsible pipelinesEric L. Hill, Mikko H. Lipasti. 553-560 [doi]
• CMOS logic design with independent-gate FinFETsAnish Muttreja, Niket Agarwal, Niraj K. Jha. 560-567 [doi]
• Distributed voting for fault-tolerant nanoscale systemsAli Namazi, Mehrdad Nourani. 568-573 [doi]
• Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuitsShu Li, Tong Zhang. 574-579 [doi]
• VIZOR: Virtually zero margin adaptive RF for ultra low power wireless communicationRajarajan Senguttuvan, Shreyas Sen, Abhijit Chatterjee. 580-586 [doi]
• Register binding guided by the size of variablesNoureddine Chabini, Wayne Wolf. 587-594 [doi]
• Power variations of multi-port routers in an application-specific NoC design : A case studyBalasubramanian Sethuraman, Ranga Vemuri. 595-600 [doi]
• System level power estimation methodology with H.264 decoder prediction IP case studyYoung-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt. 601-608 [doi]
• A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPsBita Gorjiara, Daniel Gajski. 609-614 [doi]
• Power reduction of chip multi-processors using shared resource control cooperating with DVFSRyo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya. 615-622 [doi]
• Effective Dynamic Thermal Management for MPEG-4 decodingInchoon Yeo, Heung Ki Lee, Eun Jung Kim, Ki Hwan Yum. 623-628 [doi]
• Priority-monotonic energy management for real-time systems with reliability requirementsDakai Zhu, Xuan Qi, Hakan Aydin. 629-635 [doi]
• Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipeliningMing Su, Lili Zhou, C.-J. Richard Shi. 636-643 [doi]