Abstract is missing.
- Supplemental Test Methods (Tutorial Abstract)Sreejit Chakravarty. 7 [doi]
- Design-for-Test Techniques for SoC Designs (Tutorial Abstract)Geir Eide. 7 [doi]
- Electromigration Reliability Issues in High-Performance Circuit Design (Tutorial Abstract)J. Joseph Clement. 8 [doi]
- Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract)Charvaka Duvvury. 8 [doi]
- Ultra-thin Gate Oxide Reliability and Implications for Design (Tutorial Abstract)John S. Suehle. 9 [doi]
- Power/Ground Integrity Issues for Sub-130nm IC Designs (Tutorial Abstract)Norman Chang. 10 [doi]
- MOS Modeling, Design Quality, and Modern Analog Design (Tutorial Abstract)Daniel Foty. 11 [doi]
- Platform-Based Design: A Tutorial (Tutorial Abstract)Henry Chang. 12 [doi]
- nVHDL: A Hardware Design Language for Modeling Discrete and Analog Design and Simulation of Mixed-Signal Electronic Systems (Tutorial Abstract)Sumit Ghosh. 12 [doi]
- Optimization in an Integrated Physical Design Flow (Tutorial Abstract)Olivier Coudert. 13-14 [doi]
- Quality Aspects of SOI Circuit Design (Tutorial Abstract)Andrew Marshall. 13 [doi]
- IP REUSE QUALITY: Intellectual Property or Intense Pain ?John Chilton. 21-22 [doi]
- What You Don t Know CAN Hurt You: Designing for Survival in a Sub-wavelength EnvironmentY. C. Pati. 27 [doi]
- Fabrication Technologies for Three-Dimensional Integrated Circuits (invited)Rafael Reif, Andy Fan, Kuan-Neng Chen, Shamik Das. 33-37 [doi]
- Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular MeshesVikram Jandhyala, Yong Wang, Dipanjan Gope, C.-J. Richard Shi. 38-42 [doi]
- Inductance Aware Interconnect ScalingKaustav Banerjee, Amit Mehrotra. 43-47 [doi]
- Accurate Model of Metal-Insulator-Semiconductor InterconnectsGaofeng Wang, Xiaoning Qi, Zhiping Yu, Robert W. Dutton. 48-52 [doi]
- Transition Aware Global Signaling (TAGS)Himanshu Kaul, Dennis Sylvester. 53 [doi]
- A Qualification Platform for Design ReuseRalf Seepold, Natividad Martínez Madrid, Andreas Vörg, Wolfgang Rosenstiel, Martin Radetzki, P. Neumann, J. Haase. 75-80 [doi]
- Advancing Quality of EDA Software (invited)Giora Ben-Yaacov, Pramod Suratkar, Marsha Holliday, Karen Bartleson. 81-86 [doi]
- Interoperability and Quality of New EDA Tools for Sequential Logic SynthesisAleksander Slusarczyk, Lech Józwiak. 87 [doi]
- Extending the Viability of IDDQ Testing in the Deep Submicron EraY. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni. 100-105 [doi]
- Design of Reconfigurable Access Wrappers for Embedded Core Based SoC TestSandeep Koranne. 106-111 [doi]
- Testing of Analogue Circuits via (Standard) Digital GatesDaniela De Venuto, Michael J. Ohletz, Bruno Riccò. 112-119 [doi]
- Automatic Test Program Generation from RT-Level Microprocessor DescriptionsFulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero. 120 [doi]
- Impact Analysis of Process Variability on Clock SkewEnrico Malavasi, Stefano Zanella, Min Cao, Julian Uschersohn, Mike Misheloff, Carlo Guardiani. 129-132 [doi]
- Design Method and Automation of Comparator Generation for Flash A/D ConverterDaegyu Lee, Jincheol Yoo, Kyusun Choi. 138-142 [doi]
- A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and BeyondChul-Hong Park, Soo-Han Choi, Sang-Uhk Rhie, Dong-hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong. 143-147 [doi]
- A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process SensitivitiesPrasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun. 148 [doi]
- Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex AlgorithmTing-Yuan Wang, Charlie Chung-Ping Chen. 157-162 [doi]
- Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution NetworkGeng Bai, Ibrahim N. Hajj. 163-168 [doi]
- An EMI-Noise Analysis on LSI Design with Impedance EstimationKenji Shimazaki, Shouzou Hirano, Hiroyuki Tsujikawa. 169-174 [doi]
- Chip Level Signal Integrity Analysis & Crosstalk Prediction Using Artificial Neural NetsAbby A. Ilumoka. 175-180 [doi]
- On the Use of Windows for Accurate Analysis of Package InterconnectsWendemagegnehu T. Beyene, Chuck Yuan. 181 [doi]
- Productivity Optimization Techniques for the Proactive Semiconductor Manufacturer (invited)Daniel N. Maynard. 189 [doi]
- A New Design Cost Model for the 2001 ITRS (invited)Andrew B. Kahng, Gary Smith. 190-193 [doi]
- Optimal Sequencing Energy Allocation for CMOS Integrated SystemsMartin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan. 194-199 [doi]
- Design, Manufacture and Test - Quality Test EstimationJ. M. Gilbert, Ian M. Bell, D. R. Johnson. 200-205 [doi]
- Measurement of Inherent Noise in EDA ToolsAndrew B. Kahng, Stefanus Mantik. 206-212 [doi]
- Evening Panel Discussion: Process Variation: Is It Too Much to Handle?Ron Wilson, Siva Narendra, Vivek De. 213 [doi]
- Synthesis of Selectively Clocked Skewed Logic CircuitsAiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy. 229-234 [doi]
- Low Power VLSI Architecture of Viterbi Scorer for HMM-Based Isolated Word RecognitionBok-Gue Park, Koon-Shik Cho, Jun Dong Cho. 235-239 [doi]
- On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled InterconnectsDinesh Pamunuwa, Hannu Tenhunen. 240-245 [doi]
- A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated CircuitsSyed M. Alam, Donald E. Troxel, Carl V. Thompson. 246-251 [doi]
- Reliable Laser Programmable Gate Array TechnologyZhuo Gao, Ji Luo, Hu Huang, Wei Zhang, Joseph B. Bernstein. 252-256 [doi]
- VC Rating and Quality Metrics: Why Bother?Pierre Bricaud. 257-260 [doi]
- An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BISTEmmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos. 261-266 [doi]
- An Integrated Tool for Analog Test Generation and Fault SimulationSule Ozev, Alex Orailoglu. 267-272 [doi]
- A Hybrid BIST Architecture and Its Optimization for SoC TestingGert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus. 273-279 [doi]
- Native Mode Functional Self-Test Generation for Systems-on-ChipKamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham. 280-285 [doi]
- Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs)Mandeep Singh, Israel Koren. 286-291 [doi]
- Human Immune System Inspired Architecture for Self-Healing Digital SystemsParag K. Lala, B. Kiran Kumar. 292-297 [doi]
- Impact of Low-K on CrosstalkGrégory Servel, Denis Deschacht, Françoise Saliou, Jean-Luc Mattei, Fabrice Huret. 298-303 [doi]
- Improving the Efficiency and Quality of Simulation-Based Behavioral Model Verification Using Dynamic Bayesian CriteriaAmjad Hajjar, Tom Chen. 304-309 [doi]
- In Search of the Origin of VHDL s Delta DelaysSumit Ghosh. 310-315 [doi]
- Inductive Characteristics of Power Distribution Grids in High Speed Integrated CircuitsAndrey V. Mezhiba, Eby G. Friedman. 316-321 [doi]
- Characterizing the Current Degradation of Abnormally Structured MOS Transistors Using a 3D Poisson SolverJin-Kyu Park, Keun-Ho Lee, Chang-Sub Lee, Gi-Young Yang, Young-Kwan Park, Jeong-Taek Kong. 322-325 [doi]
- AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical CorrectionsTae-young Oh, Zhiping Yu, Robert W. Dutton. 326-330 [doi]
- ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS ProcessMing-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo. 331-336 [doi]
- Design of ESD Protection Device Using Statistical MethodsNaoyuki Shigyo, Hirobumi Kawashima, Seiji Yasuda. 337-340 [doi]
- Economic Analysis of a Stopping-rule in Branch Coverage TestingMehmet Sahinoglu, Scott Glover. 341 [doi]
- Device Physics Impact on Low Leakage, High Speed DSP Design Techniques (invited)David Scott, Shaoping Tang, Song Zhao, Mahalingam Nandakumar. 349-354 [doi]
- Power Supply Noise Suppression via Clock Skew SchedulingWai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao. 355-360 [doi]
- Trading off Reliability and Power-Consumption in Ultra-low Power SystemsAtul Maheshwari, Wayne Burleson, Russell Tessier. 361-366 [doi]
- Asynchronous Circuits: An Increasingly Practical Design Solution (invited)Peter A. Beerel. 367-372 [doi]
- Trends in Low Power Digital System-on-Chip Designs (invited)Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama. 373 [doi]
- Promising Directions in Hardware Design Verification (invited)Shaz Qadeer, Serdar Tasiran. 381-387 [doi]
- Behavioral IP Specification and Integration Framework for High-Level Design ReuseSébastien Pillement, Daniel Chillet, Olivier Sentieys. 388-393 [doi]
- On the Relation between SAT and BDDs for Equivalence CheckingSherief Reda, Rolf Drechsler, Alex Orailoglu. 394-399 [doi]
- Integrated Inductors Modeling and Tools for Automatic Selection and Layout GenerationJosé R. Sendra, Javier del Pino, Antonio Hernández, Javier Hernández, Jaime Aguilera, Abdres Garcia-Alonso, Antonio Nunez. 400-404 [doi]
- Organization of a Microprocessor Design Process Using Internet-Based Interoperable WorkflowsNguyen Quang Trung, Artur Kokoszka, Krystyna Siekierska, Adam Pawlak, Dariusz Obrebski, Norbert Lugowski. 405 [doi]
- Pre-route Noise Estimation in Deep Submicron Integrated CircuitsMurat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj. 413-418 [doi]
- Time-Domain Simulation of Variational Interconnect ModelsEmrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi. 419-424 [doi]
- Noise Injection and Propagation in High Performance DesignsVladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh. 425-430 [doi]
- Efficient Closed-Form Crosstalk Delay MetricsLauren Hui Chen, Malgorzata Marek-Sadowska. 431-436 [doi]
- False-Noise Analysis Using Resolution MethodAlexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh. 437 [doi]
- Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited)Takayasu Sakurai. 445-450 [doi]
- Does Q=MC2? (On the Relationship between Quality in Electronic Design and the Model of Colloidal Computing, invited)Radu Marculescu, Diana Marculescu. 451-457 [doi]
- Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power ApplicationsGeun Rae Cho, Tom Chen. 458-463 [doi]
- Structural Decomposition with Functional Considerations for Low PowerChih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh. 464-469 [doi]
- ALBORZ: Address Level Bus Power OptimizationYazdan Aghaghiri, Farzan Fallah, Massoud Pedram. 470 [doi]
- Megagate ASICs for the Thuraya Satellite Digital Signal Processor (invited)David A. Sunderland, Gary L. Duncan, Brad J. Rasmussen, Harry E. Nichols, Daniel T. Kain, Lawrence C. Lee, Brian A. Clebowicz, Richard W. Hollis IV, Larry Wissel, Tad Wilder. 479-486 [doi]
- Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPDPin Su, Samel K. H. Fung, Weidong Liu, Chenming Hu. 487-491 [doi]
- Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate ArchitectureAdrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, P. Renaud, C. Hibert, Philippe Flückiger, G. A. Racine. 496-501 [doi]
- Single-Electronics - How It Works. How It s Used. How It s Simulated (invited)Christoph Wasshuber. 502 [doi]
- Timing and Design Closure in Physical Design Flows (invited)Olivier Coudert. 511-516 [doi]
- A Thermal-Aware Superscalar Microprocessor (invited)Chee How Lim, W. Robert Daasch, George Cai. 517-522 [doi]
- Formulae for Performance Optimization and Their Applications to Interconnect-Driven FloorplanningNicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang. 523-528 [doi]
- Hierarchical Front-End Physical Design Solution Drives Modified Hand-Off (invited)Wei-Jin Dai, Michel Courtoy. 529-533 [doi]
- Future SoC Design Challenges and Solutions (invited)Charlie Chung-Ping Chen, Ed Cheng. 534-538 [doi]