Abstract is missing.
- A New Process Variation Monitoring CircuitDavit Mirzoyan, Ararat Khachatryan. 1-5 [doi]
- Mixed-Signal Design Using Digital CADVishnu Unnikrishnan, Mark Vesterbacka. 6-11 [doi]
- An Integrated Common Gate CTLE Receiver Front End with Charge Mode AdaptationDivya Duvvuri, Vijaya Sankara Rao Pasupureddi. 12-17 [doi]
- FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and ImplementationAnupam Chattopadhyay, Vikramkumar Pudi, Anubhab Baksi, Thambipillai Srikanthan. 18-23 [doi]
- Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized HardwareKaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Song Yao, Song Han, Yu Wang, Huazhong Yang. 24-29 [doi]
- An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable FPGAsShaon Yousuf, Ann Gordon-Ross. 30-35 [doi]
- Speeding up Incremental Legalization with Fast Queries to Multidimensional TreesRenan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel. 36-41 [doi]
- Timing Analysis and Optimization Based on Flexible Flip-Flop Timing ModelJeongwoo Heo, Taewhan Kim. 42-46 [doi]
- Synthesizing Asynchronous Circuits toward Practical UseHeechun Park, Taewhan Kim. 47-52 [doi]
- Next Generation Automotive Architecture Modeling and Exploration for Autonomous DrivingBowen Zheng, Hengyi Liang, Qi Zhu, Huafeng Yu, Chung-Wei Lin. 53-58 [doi]
- Online Unusual Behavior Detection for Temperature Sensor NetworksHengyang Zhao, Sheldon X.-D. Tan, Hai Wang, Hai-Bao Chen. 59-62 [doi]
- Security Challenges in CPS and IoT: From End-Node to the SystemKelvin Ly, Yier Jin. 63-68 [doi]
- VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC ImplementationMahesh S. Murty, Rahul Shrestha. 69-74 [doi]
- Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level SynthesisAnirban Sengupta, Deepak Kachave. 75-80 [doi]
- Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane ConfigurationYaojie Lu, Seyed Amin Rooholamin, Sotirios G. Ziavras. 81-86 [doi]
- A VLSI Design for Neuromorphic ComputingMark E. Dean, Christopher Daffron. 87-92 [doi]
- Reducing the Model Order of Deep Neural Networks Using Information TheoryMing Tu, Visar Berisha, Yu Cao, Jae-sun Seo. 93-98 [doi]
- A Reconfigurable Array Architecture for NMLGiovanni Causapruno, U. Garlando, Fabrizio Cairo, Maurizio Zamboni, Mariagrazia Graziano. 99-104 [doi]
- Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect TransistorS. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin. 105-109 [doi]
- A Memristor Crossbar Based Computing Engine Optimized for High Speed and AccuracyChenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li. 110-115 [doi]
- Design of Division Circuits for Stochastic ComputingTe-Hsuan Chen, John P. Hayes. 116-121 [doi]
- Adaptive Filter Design Using Stochastic CircuitsHonglan Jiang, Chengkun Shen, Pieter P. Jonker, Fabrizio Lombardi, Jie Han. 122-127 [doi]
- High-Accuracy FIR Filter Design Using Stochastic ComputingBo Yuan, Yanzhi Wang. 128-133 [doi]
- Design and Characterization of the TERO-PUF on SRAM FPGAsCédric Marchand 0002, Lilian Bossuet, Abdelkarim Cherkaoui. 134-139 [doi]
- Hardware/Software Isolation and Protection Architecture for Transparent Security Enforcement in Networked DevicesFestus Hategekimana, Pierre Nardin, Christophe Bobda. 140-145 [doi]
- A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare CoreB. Naresh Kumar Reddy, M. H. Vasantha, Kumar Y. B. Nithin. 146-151 [doi]
- Analyzing Imprecise Adders Using BDDs - A Case StudyCunxi Yu, Maciej J. Ciesielski. 152-157 [doi]
- Post-Placement Optimization for Thermal-Induced Mechanical Stress ReductionTiantao Lu, Zhiyuan Yang, Ankur Srivastava. 158-163 [doi]
- Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT ConfigurationsAmit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell. 164-169 [doi]
- Low Cost VLSI Architecture for Sample Adaptive Offset Encoder in HEVCSayed El Gendy, Ahmed Shalaby, Mohammed S. Sayed. 170-175 [doi]
- Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUsYaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu. 176-181 [doi]
- Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and CellsWeiwei Shi, Zhao Guangdong, Oliver Chiu-sing Choy. 182-187 [doi]
- Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs)Hao-Ting Shen, Fahim Rahman, Bicky Shakya, Mark Tehranipoor, Domenic Forte. 188-193 [doi]
- A Designer's Rationale for Nanoelectronic Hardware Security PrimitivesGarrett S. Rose, Mesbah Uddin, Md. Badruddoja Majumder. 194-199 [doi]
- Hardware Security Challenges Beyond CMOS: Attacks and RemediesKaveh Shamsi, Wujie Wen, Yier Jin. 200-205 [doi]
- Attacking an SRAM-Based PUF through WearoutAlec Roelke, Mircea R. Stan. 206-211 [doi]
- Techniques for Improved Reliability in Memristive Crossbar PUF CircuitsMesbah Uddin, Md. Badruddoja Majumder, Garrett S. Rose, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady. 212-217 [doi]
- LLPA: Logic State Based Leakage Power AnalysisSiva Nishok Dhanuskodi, Shahrzad Keshavarz, Daniel Holcomb. 218-223 [doi]
- Hardware Design Automation of Convolutional Neural NetworksAndrea Solazzo, Emanuele Del Sozzo, Irene De Rose, Matteo De Silvestri, Gianluca C. Durelli, Marco D. Santambrogio. 224-229 [doi]
- Low-Power Wearable System for Real-Time Screening of Obstructive Sleep ApneaGregoire Surrel, Francisco J. Rincón, Srinivasan Murali, David Atienza. 230-235 [doi]
- YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary WeightsRenzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini. 236-241 [doi]
- Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUsKapil Dev, Sherief Reda, Indrani Paul, Wei Huang, Wayne Burleson. 242-247 [doi]
- Write Pulse Scaling for Energy Efficient STT-MRAMYousra Alkabani, Zach Koopmans, Haifeng Xu, Alex K. Jones, Rami G. Melhem. 248-253 [doi]
- Hardware Trust through Layout Filling: A Hardware Trojan Prevention TechniquePapa-Sidi Ba, Sophie Dupuis, Palanichamy Manikandan, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. 254-259 [doi]
- Computing in Ribosomes: Performing Boolean Logic Using mRNA-Ribosome SystemPratima Chatterjee, Mayukh Sarkar, Prasun Ghosal. 260-265 [doi]
- Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAMBohua Li, Yukui Pei, Wujie Wen. 266-271 [doi]
- System Design for In-Hardware STDP Learning and Spiking Based Probablistic InferenceKhadeer Ahmed, Amar Shrestha, Yanzhi Wang, Qinru Qiu. 272-277 [doi]
- A Hybrid Algorithm to Conservatively Check the Robustness of CircuitsNiels Thole, Görschwin Fey, Alberto García Ortiz. 278-283 [doi]
- Formal Verification Using Don't-Care and Vanishing PolynomialsCunxi Yu, Maciej J. Ciesielski. 284-289 [doi]
- Routing-Aware Incremental Timing-Driven PlacementJucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Augusto da Luz Reis, Andrew A. Kennings, Marcelo de Oliveira Johann, Laleh Behjat. 290-295 [doi]
- Design and Performance Evaluation of Approximate Floating-Point MultipliersPeipei Yin, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi. 296-301 [doi]
- Energy-Efficient Design of the Secure Better Portable Graphics Compression Architecture for Trusted Image Communication in the IoTUmar Albalawi, Saraju P. Mohanty, Elias Kougianos. 302-307 [doi]
- Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic LogicS. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad, Vijay Singh, Kalyan S. Perumalla. 308-313 [doi]
- Scalable Integer DCT Architecture for HEVC EncoderMaher Abdelrasoul, Mohammed S. Sayed, Victor Goulart. 314-318 [doi]
- An Improved Approach for the Synthesis of Boolean Functions Using Memristor Based IMPLY and INVERSE-IMPLY GatesF. Lalchhandama, Brojo Gopal Sapui, Kamalika Datta. 319-324 [doi]
- Adaptive Overclocking and Error Correction Based on Dynamic Speculation WindowRengarajan Ragavan, Cedric Killian, Olivier Sentieys. 325-330 [doi]
- On-Chip Delay Measurement Circuit for Reliability Characterization of SRAMPankaj Verma, Rohit Halba, Hemant Patel, Maryam Shojaei Baghini. 331-336 [doi]
- Digital LDO with Time-Interleaved Comparators for Fast Response and Low RippleSaurav Maji, Sohail Ahasan, Saurav Maji, Kaushik Roy 0001, Mrigank Sharad. 337-342 [doi]
- Design of Low Power 5-Bit Hybrid Flash ADCS. M. Mayur, R. K. Siddharth, Kumar Y. B. Nithin, M. H. Vasantha. 343-348 [doi]
- An Accurate All CMOS Temperature Sensor for IoT ApplicationsSunil Kumar Maddikatla, Srivatsava Jandhyala. 349-354 [doi]
- Design of Low-Power High-Gain Operational Amplifier for Bio-Medical ApplicationsSanjay Singh Rajput, Ashish Singh, Ashwani Kumar Chandel, Rajeevan Chandel. 355-360 [doi]
- A Compact Set of Seeds for LFSR-Based Test Generation from a Fully-Specified Compact Test SetIrith Pomeranz. 361-366 [doi]
- Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit DesignRaghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas. 367-372 [doi]
- Approximate Adder with Hybrid Prediction and Error Compensation TechniqueXinghua Yang, Yue Xing, Fei Qiao, Qi Wei, Huazhong Yang. 373-378 [doi]
- SecCheck: A Trustworthy System with Untrusted ComponentsRajshekar Kalayappan, Smruti R. Sarangi. 379-384 [doi]
- A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance AnalysisYuanchang Chen, Xinghua Yang, Fei Qiao, Jie Han, Qi Wei, Huazhong Yang. 385-390 [doi]
- On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAsMarek Parfieniuk, Sang Yoon Park. 391-396 [doi]
- Phase-Based Dynamic Instruction Window Optimization for Embedded SystemsTosiron Adegbija, Ann Gordon-Ross. 397-402 [doi]
- Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit TechnologyMingyu Li, Jiajun Shi, Mostafizur Rahman, Santosh Khasanvis, Sachin Bhat, Csaba Andras Moritz. 403-408 [doi]
- Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAMKibum Lee, S. Simon Wong. 409-414 [doi]
- Accurate Synthesis of Arithmetic Operations with Stochastic LogicEnsar Vahapoglu, Mustafa Altun. 415-420 [doi]
- A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS TechnologyMahdi Elghazali, Manoj Sachdev, Ajoy Opal. 421-425 [doi]
- Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPsSheng Liu, Haiyan Chen, Jianghua Wan, Yaohua Wang. 426-430 [doi]
- Energy Optimization of Racetrack Memory-Based SIMON Block CipherSuman Deb, Anupam Chattopadhyay, Hao Yu. 431-436 [doi]
- Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar ArraysMuhammed Ceylan Morgul, Furkan Peker, Mustafa Altun. 437-442 [doi]
- Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering AttacksMaria I. Mera Collantes, Mohamed El Massad, Siddharth Garg. 443-448 [doi]
- On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICsJiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Csaba Andras Moritz. 449-454 [doi]
- A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film TransistorsNan Wu, Zheyu Liu, Fei Qiao, Qi Wei, Xiaojun Guo, Yuan Xie 0001, Huazhong Yang. 455-460 [doi]
- A Configurable and Lightweight Timing Monitor for Fault Attack DetectionChinmay Deshpande, Bilgiday Yuce, Nahid Farhady Ghalaty, Dinesh Ganta, Patrick Schaumont, Leyla Nazhandali. 461-466 [doi]
- Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI CircuitsAndrew Whetzel, Mircea R. Stan. 467-472 [doi]
- Analysis of Switching Energy and Delay for Magnetic Logic DevicesMadhav Rao, Neha Oraon. 473-478 [doi]
- A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication SystemsPo Tsang Chen, Ching-Yuan Yang. 479-483 [doi]
- A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance ConstraintsIoannis S. Stamelakos, Amin Khajeh, Ahmed M. Eltawil, Gianluca Palermo, Cristina Silvano, Fadi J. Kurdahi. 484-489 [doi]
- Fault-Tolerant Clock Synchronization with High PrecisionAttila Kinali, Florian Huemer, Christoph Lenzen. 490-495 [doi]
- STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC DesignAvik Bose, Prasun Ghosal, Saraju P. Mohanty. 496-501 [doi]
- Leveraging Compiler Support on VLIW Processors for Efficient Power GatingJuan S. P. Giraldo, Luigi Carro, Stephan Wong, Antonio C. S. Beck. 502-507 [doi]
- MINLP Based Power Optimization for Pipelined ADCA. Purushothaman. 508-511 [doi]
- Voice Based User-Device Physical Unclonable Functions for Mobile Device AuthenticationYunxi Guo, Akhilesh Tyagi. 512-517 [doi]
- Taylor Series Based Architecture for Quadruple Precision Floating Point DivisionManish Kumar Jaiswal, Hayden Kwok-Hay So. 518-523 [doi]
- An Accurate All CMOS Bandgap Reference Voltage with Integrated Temperature Sensor for IoT ApplicationsSunil Kumar Maddikatla, Srivatsava Jandhyala. 524-528 [doi]
- Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICsKanchan Manna, Chatla Swamy Sagar, Santanu Chattopadhyay, Indranil Sengupta 0001. 529-534 [doi]
- Design Optimization of Register File Throughput and Energy Using a Virtual Prototyping (ViPro) ToolNingxi Liu, Benton H. Calhoun. 535-540 [doi]
- A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based AttacksXuanle Ren, Ronald D. Blanton, Vitor Grade Tavares. 541-546 [doi]
- Using Statistical Models to Improve the Reliability of Delay-Based PUFsXiaolin Xu, Wayne Burleson, Daniel E. Holcomb. 547-552 [doi]
- Fast Multi-level Test Generation at the RTLKelson Gent, Michael S. Hsiao. 553-558 [doi]
- Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific AcceleratorMaria Malik, Farnoud Farahmand, Paul Otto, Nima Akhlaghi, Tinoosh Mohsenin, Siddhartha Sikdar, Houman Homayoun. 559-564 [doi]
- DSD: A Dynamic State-Deflection Method for Gate-Level Netlist ObfuscationJaya Dofe, Yuejun Zhang, Qiaoyan Yu. 565-570 [doi]
- Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience TradeoffsFaris S. Alghareb, Mingjie Lin, Ronald F. DeMara. 571-576 [doi]
- Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder CircuitsVinamra Benara, Suresh Purini. 577-582 [doi]
- Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-ChipKanchan Manna, Santanu Chattopadhyay, Indranil Sengupta 0001. 583-586 [doi]
- A Low-Cost Mixed Clock Generator for High Speed Adiabatic LogicZhou Zhao, Ashok Srivastava, Lu Peng, Saraju P. Mohanty. 587-590 [doi]
- Accelerating Particle Filter on FPGAB. G. Sileshi, Juan Oliver, C. Ferrer. 591-594 [doi]
- Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between ComponentsJunghoon Oh, Mineo Kaneko. 595-600 [doi]
- Gossip NoC - Avoiding Timing Side-Channel Attacks through Traffic ManagementCezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Johanna Sepúlveda. 601-606 [doi]
- Leakage Power Aware Task Assignment Algorithms for Multicore PlatformsGayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan. 607-612 [doi]
- A Design Space Exploration Methodology for Parameter Optimization in Multicore ProcessorsPrasanna Kansakar, Arslan Munir. 613-618 [doi]
- Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant GraphsZheng Wang 0020, Alessandro Littarru, Emmanuel Ikechukwu Ugwu, Shazia Kanwal, Anupam Chattopadhyay. 619-624 [doi]
- Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its ApplicationsTso-Bing Juang, Ying-Ren Lee. 625-630 [doi]
- On Time Redundancy of Fault Tolerant C-Based MPSoCsAnjana Balachandran, Nandeesh Veeranna, Benjamin Carrión Schäfer. 631-636 [doi]
- Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design SpaceDylan Stow, Itir Akgun, Russell Barnes, Peng Gu, Yuan Xie 0001. 637-642 [doi]
- Memristor-Based Discrete Fourier Transform for Improving Performance and Energy EfficiencyRuizhe Cai, Ao Ren, Yanzhi Wang, Bo Yuan. 643-648 [doi]
- Device Circuit Co Design of FEFET Based Logic for Low Voltage ProcessorsSumitha George, Ahmedullah Aziz, Xueqing Li, Moon Seok Kim, Suman Datta, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan. 649-654 [doi]
- A Scalable Design Approach to Efficiently Map Applications on CGRAsSatyajit Das, Thomas Peyret, Kevin Martin, Gwenolé Corre, Mathieu Thevenin, Philippe Coussy. 655-660 [doi]
- SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA FlowTan Nguyen, Yao Chen, Kyle Rupnow, Swathi T. Gurumani, Deming Chen. 661-666 [doi]
- Area Efficient Hardware Architecture for Implicitly-Defined Complex Events ProcessingMohammad Tahghighi, Wei Zhang, Sharad Sinha. 667-672 [doi]
- Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell LibraryChi-Hung Lin, Chia-Shiang Chen, Yu-He Chang, Yu Ting Zhang, Shang-Rong Fang, Santanu Santra, Rung-Bin Lin. 673-678 [doi]
- Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAMInfall Syafalni, Tsutomu Sasao, Xiaoqing Wen. 679-684 [doi]
- A Comparative Study of Si/Ge and GaSb/InAs Tunnel FET-Based Cellular Neural NetworkAmit Ranjan Trivedi, Susmita Dey Manasi. 685-690 [doi]
- A Dual-Threshold Voltage Approach for Timing Speculation in CMOS CircuitsXiaowen Wang, William H. Robinson. 691-696 [doi]
- Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and InterconnectOana Boncalo, Ioana Mot. 697-700 [doi]
- The Impact of Heterogeneity on a Reconfigurable Multicore SystemRafael Fao de Moura, Jeckson Dellagostin Souza, Luigi Carro, Antonio Carlos Schneider Beck, Mateus Beck Rutzig. 701-706 [doi]
- A Pruning Technique for B&B Based Design Exploration of Approximate Computing VariantsMario Barbareschi, Federico Iannucci, Antonino Mazzeo. 707-712 [doi]
- Stochastic-Based Convolutional Networks with Reconfigurable Logic FabricMohammed Alawad, Mingjie Lin. 713-718 [doi]
- A Ternary-Valued, Floating Gate Transistor-Based Circuit Design ApproachMonther Abusultan, Sunil P. Khatri. 719-724 [doi]
- Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time VariabilityInnocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor, Wim Dehaene. 725-730 [doi]
- Improving the Functional Test Delay Fault Coverage: A Microprocessor Case StudyAymen Touati, Alberto Bosio, Patrick Girard 0001, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda. 731-736 [doi]
- Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential ElementsJi Li, Jeffrey T. Draper. 737-742 [doi]