Abstract is missing.
- Towards reverse engineering the brain: Modeling abstractions and simulation frameworksJayram Moorkanikara Nageswaran, Micah Richert, Nikil D. Dutt, Jeffrey L. Krichmar. 1-6 [doi]
- Synchronous elasticization: Considerations for correct implementation and MiniMIPS case studyEliyah Kilada, Shomit Das, Kenneth S. Stevens. 7-12 [doi]
- A fault-aware, reconfigurable and adaptive routing algorithm for NoC applicationsMojtaba Valinataj, Siamak Mohammadi. 13-18 [doi]
- TM-FAR: Turn-Model based Fully Adaptive Routing for Networks on ChipWen-Chung Tsai, Kuo-Chih Chu, Sao-Jie Chen, Yu Hen Hu. 19-24 [doi]
- A binary adaptable window SoC architecture for a stereo vision based depth field processorAndy Motten, Luc Claesen. 25-30 [doi]
- Network interface to synchronize multiple packets on NoC-based Systems-on-ChipDebora Matos, Miklecio Costa, Luigi Carro, Altamiro Amadeu Susin. 31-36 [doi]
- Order is power: Selective Packet Interleaving for energy efficient Networks-on-ChipAmit Berman, Ran Ginosar, Idit Keidar. 37-42 [doi]
- Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyperPaolo Meloni, Simone Secchi, Luigi Raffo. 43-48 [doi]
- SoCGuard: A runtime verification solution for the functional correctness of SoCsRawan Abdel-Khalek, Valeria Bertacco. 49-54 [doi]
- Enhancing post-silicon processor debug with Incremental Cache state DumpingPreeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan. 55-60 [doi]
- Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesisNicola Bombieri, Franco Fummi, Valerio Guarnieri. 61-66 [doi]
- Power-aware FPGA routing fabrics and design toolsShoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 67-72 [doi]
- Fine-grained post placement voltage assignment considering level shifter overheadZohreh Karimi, Majid Sarrafzadeh. 73-78 [doi]
- A new software tool for static analysis of SET sensitiveness in Flash-based FPGAsNiccolò Battezzati, Luca Sterpone, Massimo Violante, Filomena Decuzzi. 79-84 [doi]
- Reduction of process variation effect on FPGAs using multiple configurationsDelasa Aghamirzaie, Seyyed Ahmad Razavi, Morteza Saheb Zamani, Mahdi Nabiyouni. 85-90 [doi]
- An optimized lookup-table for the evaluation of sigmoid function for artificial neural networksPramod Kumar Meher. 91-95 [doi]
- Synchronous duty cycle correction circuitSergey Sofer, Valery Neiman, Eyal Melamed-Cohen. 96-100 [doi]
- An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detectorDing-Guo Lin, Bing-Hsun Lu, Herming Chiueh. 101-104 [doi]
- Spatial EM jamming: A countermeasure against EM Analysis?Francois Poucheret, Lyonel Barthe, Pascal Benoit, Lionel Torres, Philippe Maurine, Michel Robert. 105-110 [doi]
- Ultra low voltage and high speed CMOS flip-flop using floating-gatesYngvar Berg. 111-114 [doi]
- Static ultra-low-voltage high-speed CMOS logic and latchesYngvar Berg. 115-118 [doi]
- An improved RNS generator 2:::n::: +/- k based on threshold logicHéctor Pettenghi, Ricardo Chaves, Leonel Sousa, Maria J. Avedillo. 119-124 [doi]
- Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systemsJongpil Jung, Seonpil Kim, Chong-Min Kyung. 125-130 [doi]
- Optimal scheduling to minimize non-volatile memory access time with hardware cacheWei-Che Tseng, Chun Jason Xue, Qingfeng Zhuge, Jingtong Hu, Edwin Hsing-Mean Sha. 131-136 [doi]
- A reconfigurable MPSoC-based QAM modulation architectureC. Ttofis, A. Papadopoulos, Theocharis Theocharides, M. Michael, D. Doumenis. 137-142 [doi]
- Design and implementation of MPSoC single chip with butterfly networkKhawla Hamwi, Omar Hammami. 143-148 [doi]
- Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICsFengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici. 149-154 [doi]
- An automatic framework for dynamic data structures optimization in CChristos Baloukas, Lazaros Papadopoulos, Robert Pyka, Dimitrios Soudris, Peter Marwedel. 155-160 [doi]
- Adaptive logical control of RF LNA performances for efficient energy consumptionRafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni. 161-166 [doi]
- A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band controlHui Shao, Chi-Ying Tsui, Wing-Hung Ki. 167-172 [doi]
- A high-speed high-resolution low-phase noise oscillator using self-timed ringsOussama Elissati, Eslam Yahya, Sebastien Rieubon, Laurent Fesquet. 173-178 [doi]
- A highly linear wide dynamic range detector for cell recording with microelectrode arraysJing Guo, Bing Liu, Jie Yuan. 179-182 [doi]
- A 1mm:::2::: 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOSC. Benkeser, A. Bubenhofer, Q. Huang. 183-188 [doi]
- Area- and throughput-optimized VLSI architecture of sphere decodingMarkus Wenk, Lukas Bruderer, Andreas Burg, Christoph Studer. 189-194 [doi]
- Fast fixed-point optimization of DSP algorithmsGabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero. 195-200 [doi]
- Novel input coding technique for high-precision LUT-based multiplication for DSP applicationsPramod Kumar Meher. 201-206 [doi]
- An adaptive bilateral motion estimation algorithm and its hardware architectureAbdulkadir Akin, Mert Cetin, Burak Erbagci, Ozgur Karakaya, Ilker Hamzaoglu. 207-212 [doi]
- A decimal squarer with efficient partial product generationKuan Jen Lin, Yu Chan Chiu, Tzu-Hao Lin. 213-218 [doi]
- Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(p:::m:::)Somsubhra Talapatra, Hafizur Rahaman. 219-224 [doi]
- Novel ultra low-voltage and high speed domino CMOS logicYngvar Berg. 225-228 [doi]
- High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulationsRoman Plyaskin, Alejandro Masrur, Martin Geier, Samarjit Chakraborty, Andreas Herkersdorf. 229-234 [doi]
- Timing and interface communication analysis of H.264/AVC encoder using SystemC modelBruno Zatt, Cláudio Machado Diniz, Luciano Volcan Agostini, Sergio Bampi. 235-240 [doi]
- Control electronics integration toward endoscopic capsule robot performing legged locomotion and illuminationOscar Alonso, L. Freixas, Joan Canals, Ekawahyu Susilo, A. Diéguez. 241-246 [doi]
- Smart camera SoC system for interactive real-time real-brush based digital painting systemsLuc Claesen, Peter Vandoren, Tom Van Laerhoven, Andy Motten, Domien Nowicki, Tom De Weyer, Frank Van Reeth, Eddy Flerackers. 247-252 [doi]
- A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOSJoachim Neves Rodrigues, Omer Can Akgun, Viktor Öwall. 253-258 [doi]
- Supporting circuitry for a fully integrated micro electro mechanical (MEMS) oscillator in 45 nm CMOS technologyM. Abdelsalam, M. Wahba, M. Abdelmoneum, D. Duarte, Yehia Ismail. 259-263 [doi]
- Energy aware multimodal embedded video surveillanceMichele Magno, Alessandro Lanza, Davide Brunelli, Luigi di Stefano, Luca Benini. 264-269 [doi]
- Towards sustainable exascale computingRoberto Gioiosa. 270-275 [doi]
- Trends and techniques for energy efficient architecturesVictor Jimenez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero. 276-279 [doi]
- Logic synthesis and testability of D-reducible functionsAnna Bernasconi, Valentina Ciriani. 280-285 [doi]
- On the synthesis of attack tolerant cryptographic hardwareJimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir. 286-291 [doi]
- Design of low-complexity and high-speed digital Finite Impulse Response filtersDiego Jaccottet, Eduardo Costa, Levent Aksoy, Paulo F. Flores, Josee Monteiro. 292-297 [doi]
- A broad strategy to detect crosstalk faults in network-on-chip interconnectsMariza Botelho, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Érika F. Cota, Luigi Carro. 298-303 [doi]
- A low-power, high-speed DCT architecture for image compression: Principle and implementationMaher Jridi, Ayman Alfalou. 304-309 [doi]
- Fast forward and inverse transforms for the H.264/AVC standard using hierarchical adder compressorsJoao S. Altermann, Eduardo A. C. da Costa, Sergio Bampi. 310-315 [doi]
- Hardware integrated quantization solution for improvement of computational H.264 encoder moduleRonaldo Husemann, Mariano Majolo, Victor Guimaraes, Altamiro Amadeu Susin, Valter Roesler, José Valdeni de Lima. 316-321 [doi]
- Architectural synthesis of DSP circuits under simultaneous error and time constraintsGabriel Caffarena, Carlos Carreras. 322-327 [doi]
- Output probability density functions of logic circuits: Modeling and fault-tolerance evaluationMilos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici. 328-334 [doi]
- VCTA: A Via-Configurable Transistor Array regular fabricMarc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González. 335-340 [doi]
- SESAM extension for fast MPSoC architectural exploration and dynamic streaming applicationsNicolas Ventroux, T. Sassolas, Raphael David, G. Blanc, Alexandre Guerre, C. Bechara. 341-346 [doi]
- Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuitsHailong Jiao, Volkan Kursun. 347-351 [doi]
- Temperature- and bus traffic- aware data placement in 3D-stacked cacheSeunghan Lee, Kyungsu Kang, Chong-Min Kyung. 352-357 [doi]
- Power-aware partitioning of data convertersAlberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii. 358-363 [doi]
- 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XORNazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. 364-368 [doi]
- Fast legalization for standard cell placement with simultaneous wirelength and displacement minimizationTsung-Yi Ho, Sheng-Hung Liu. 369-374 [doi]
- Characterization of chip-to-chip wireless interconnections based on capacitive couplingR. Cardu, Eleonora Franchi, Roberto Guerrieri, Mauro Scandiuzzo, S. Cani, L. Perugini, S. Spolzino, Roberto Canegallo. 375-380 [doi]
- A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output poleAaron V. Do, C. C. Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk. 381-386 [doi]
- A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4M. Vamshi Krishna, J. Xie, M. A. Do, C. C. Boon, K. S. Yeo, Aaron V. Do. 387-391 [doi]
- A 36-mW continuous-time sigma-delta modulator with 74db dynamic range and 10-MHz bandwidthKuo-Che Hong, Herming Chiueh. 392-395 [doi]
- Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurationsChengmo Yang, Alex Orailoglu. 396-401 [doi]
- A novel reconfigurable scratchpad memory for audio applications on cost-effective SoCJi Kong, Peilin Liu. 402-407 [doi]
- Unifying stream based and reconfigurable computing to design application acceleratorsBruno Francisco, Frederico Pratas, Leonel Sousa. 408-413 [doi]
- A design workflow for dynamically reconfigurable multi-FPGA systemsAlessandro Panella, Marco D. Santambrogio, Francesco Redaelli, Fabio Cancare, Donatella Sciuto. 414-419 [doi]
- Fine-grained adaptive CMP cache sharing through access history exploitationChengmo Yang, Chun Jason Xue, Alex Orailoglu. 420-425 [doi]