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Viewing Publication 1 - 100 from 848

1996

KIR - a graph-based model for description of mixed analog/digital systemsChristoph Grimm 0001, Klaus Waldschmidt. eurodac 1996: 568-573 [doi]

Exploration of hardware/software design space through a codesign of robot arm controllerMohamed Abid, Adel Changuel, Ahmed Amine Jerraya. eurodac 1996: 42-47 [doi]

TINA: analog placement using enumerative techniques capable of optimizing both area and net lengthTobias H. Abthoff, Frank M. Johannes. eurodac 1996: 398-403 [doi]

A hierarchical approach to analog behavioral modeling of neural networks using HDL-AM. Ahmed, H. F. Ragaie, H. Haddara. eurodac 1996: 2-9 [doi]

Global stacking for analog circuitsBogdan G. Arsintescu, Sorin A. Spânoche. eurodac 1996: 392-397 [doi]

The maximal VHDL subset with a cycle-level abstractionWendell C. Baker, A. Richard Newton. eurodac 1996: 470-475 [doi]

Component selection in resource shared and pipelined DSP applicationsSmita Bakshi, Daniel D. Gajski, Hsiao-Ping Juan. eurodac 1996: 370-375 [doi]

Modeling ASIC memories in VHDLEkambaram Balaji, Prabhu Krishnamurthy. eurodac 1996: 502-508 [doi]

A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuitsPeter A. Beerel, Wei-Chun Chou, Kenneth Y. Yun. eurodac 1996: 284-289 [doi]

MILP based task mapping for heterogeneous multiprocessor systemsArmin Bender. eurodac 1996: 190-197 [doi]

Synchronous parallel controller synthesis from behavioural multiple-process VHDL descriptionKrzysztof Bilinski, Erik L. Dagless, Jaroslaw Mirkowski. eurodac 1996: 516-521 [doi]

Specification and design of electronic control unitsJürgen Bortolazzi, Thomas Hirth, Thomas Raith. eurodac 1996: 36-41 [doi]

BRASIL: the Braunschweig mixed-mode-simulator for integrated circuitsUlrich Bretthauer, Ernst-Helmut Horneber. eurodac 1996: 10-14 [doi]

A refinement calculus for VHDLPeter T. Breuer, Carlos Delgado Kloos, Natividad Martínez Madrid, Luis Sánchez, Andrés Marín. eurodac 1996: 482-487 [doi]

Library based technology mapping using multiple domain representationsJ. Bullmann, Wolfgang Rosenstiel, E. Schubert, Udo Kebschull. eurodac 1996: 146-150 [doi]

Spotlights on recent developments in microsystem technologyStephanus Büttgenbach. eurodac 1996: 274-279 [doi]

Incremental re-encoding for symbolic traversal of product machinesGianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich. eurodac 1996: 158-163 [doi]

Design of an adaptive motors controller based on fuzzy logic using behavioral synthesisAdel Changuel, Ahmed Amine Jerraya, Robin Rolland. eurodac 1996: 48-52 [doi]

VHDL 1076.1 - analog and mixed signal extensions to VHDLErnst Christen, Kenneth Bakalar. eurodac 1996: 556-561 [doi]

Controller optimization for protocol intensive applicationsAndrew Crews, Forrest Brewer. eurodac 1996: 140-145 [doi]

Specification and management of timing constraints in behavioral VHDLFrancesco Curatelli, Marco Chirico, Leonardo Mangeruca. eurodac 1996: 522-527 [doi]

Timing verification for asynchronous designRhodri M. Davies, John V. Woods. eurodac 1996: 78-83 [doi]

Model generation of test logic for macrocell based designsEduardo de la Torre, J. Calvo, Javier Uceda. eurodac 1996: 456-461 [doi]

Generalized coupling as a way to improve the convergence in relaxation-based solversVladimir B. Dmitriev-Zdorov. eurodac 1996: 15-20 [doi]

Automatic structuring and optimization of hierarchical designsHeinz-Josef Eikerling, Wolfgang Rosenstiel. eurodac 1996: 134-139 [doi]

Hardware/software partitioning of VHDL system specificationsPetru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli. eurodac 1996: 434-439 [doi]

Timing optimization by an improved redundancy addition and removal techniqueLuis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo. eurodac 1996: 342-347 [doi]

EXPLORER: an interactive floorplanner for design space explorationHenrik Esbensen, Ernest S. Kuh. eurodac 1996: 356-361 [doi]

An integrated approach to engineering computer systemsD. Gareth Evans, Peter N. Green, Derrick Morris. eurodac 1996: 264-269 [doi]

Hardware synthesis from requirement specificationsKonrad Feyerabend, Rainer Schlör. eurodac 1996: 496-501 [doi]

Assignment of storage values to sequential read-write memoriesSabih H. Gerez, Erwin G. Woutersen. eurodac 1996: 302-307 [doi]

An extendable MIPS-I processor kernel in VHDL for hardware/software co-designMichael Gschwind, Dietmar Maurer. eurodac 1996: 548-553 [doi]

MORE: an alternative implementation of BDD packages by multi-operand synthesisAndreas Hett, Bernd Becker, Rolf Drechsler. eurodac 1996: 164-169 [doi]

Estimation of the number of routing layers and total wirelength in a PCB through wiring distribution analysisIvan Hom, John J. Granacki. eurodac 1996: 310-315 [doi]

Compilation of optimized OBDD-algorithmsStefan Höreth. eurodac 1996: 152-157 [doi]

A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUsMasaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi. eurodac 1996: 126-131 [doi]

Clock optimization for high-performance pipelined designHsiao-Ping Juan, Smita Bakshi, Daniel D. Gajski. eurodac 1996: 330-335 [doi]

COMET: a hardware-software codesign methodologyMichael J. Knieser, Christos A. Papachristou. eurodac 1996: 178-183 [doi]

State assignment for FSM low power designManfred Koegst, Klaus Feske, Günter Franke. eurodac 1996: 28-33 [doi]

Testable path delay fault cover for sequential circuitsAngela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar. eurodac 1996: 220-226 [doi]

Efficient random testing with global weightsArno Kunzmann. eurodac 1996: 227-232 [doi]

A VHDL reuse workbenchGunther Lehmann, Klaus D. Müller-Glaser, Bernhard Wunder. eurodac 1996: 412-417 [doi]

Instruction selection for embedded DSPs with complex instructionsRainer Leupers, Peter Marwedel. eurodac 1996: 200-205 [doi]

Storage optimization by replacing some flip-flops with latchesYoun-Long Lin, Tsung-Yi Wu. eurodac 1996: 296-301 [doi]

BDD-based testability estimation of VHDL designsEnrico Macii, Massimo Poncino, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto. eurodac 1996: 444-449 [doi]

A graphical data management system for HDL-based ASIC design projectsClaus Mayer, Jörg Pleickhardt, Hans Sahm. eurodac 1996: 92-97 [doi]

Synthesis from mixed specificationsGiovanni De Micheli, Vincnet J. Mooney III, Claudionor Nunes Coelho, Toshiyuki Sakamoto. eurodac 1996: 114-119 [doi]

Physical design CAD in deep sub-micron eraTakashi Mitsuhashi, Masami Murakata, Kenji Yoshida, T. Aoki. eurodac 1996: 350-355 [doi]

Describing space-continuous models of microelectromechanical devices for behavioral simulationZeljko Mrcarica, Helmut Detter, D. Glozic, Vanco B. Litovski. eurodac 1996: 316-321 [doi]

A top down mixed-signal design methodology using a mixed-signal simulator and analog HDLT. Murayama, Y. Gendai. eurodac 1996: 59-64 [doi]

CAD of microsystems - a challenge for system engineeringKlaus D. Müller-Glaser. eurodac 1996: 280-281 [doi]

Rapid performance estimation for system designSanjiv Narayan, Daniel D. Gajski. eurodac 1996: 206-211 [doi]

Towards maximising the use of structural VHDL for synthesisKevin O'Brien, Serge Maginot, Anne Robert. eurodac 1996: 528-533 [doi]

False path exclusion in delay analysis of RTL-based datapath-controller designsChristos A. Papachristou, Mehrdad Nourani. eurodac 1996: 336-341 [doi]

Module assignment for low powerMassoud Pedram, Jui-Ming Chang. eurodac 1996: 376-381 [doi]

Hardware/software-cosimulation for mechatronic system designGeorg Pelz, Jürgen Bielefeld, Günther Hess, Günter Zimmer. eurodac 1996: 246-251 [doi]

Fault tolerant and BIST design of a FIFO cellPaolo Prinetto, Fulvio Corno, Matteo Sonza Reorda. eurodac 1996: 233-238 [doi]

Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experimentPaolo Prinetto, Alfredo Benso, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Arturo M. Amendola, Leonardo Impagliazzo, P. Marmo. eurodac 1996: 536-541 [doi]

Decomposed symbolic forward traversals of large finite state machinesStefano Quer, Gianpiero Cabodi, Paolo Camurati. eurodac 1996: 170-175 [doi]

New approach in gate-level glitch modellingDirk Rabe, Wolfgang Nebel. eurodac 1996: 66-71 [doi]

Analysis of different protocol description styles in VHDL for high-level synthesisMaher Rahmouni, Ahmed Amine Jerraya, Polen Kission, Antônio C. Mesquita, Aloysio Pedroza, Luci Pirmez. eurodac 1996: 490-495 [doi]

Beyond VHDL: textual formalisms, visual techniques, or both?Franz J. Rammig. eurodac 1996: 420-427 [doi]

A fault model for VHDL descriptions at the register transfer levelTeresa Riesgo, Javier Uceda. eurodac 1996: 462-467 [doi]

A digital method for testing embedded switched capacitor filtersM. Robson, G. Russell. eurodac 1996: 239-244 [doi]

An integrated concept for design project planning and design flow controlMichael Ryba, Utz G. Baitinger. eurodac 1996: 98-103 [doi]

Implementing fuzzy control systems using VHDL and statechartsValentina Salapura, Volker Hamann. eurodac 1996: 53-58 [doi]

A high-level synthesis approach to optimum design of self-checking circuitsMariagiovanna Sami, Anna Antola, Vincenzo Piuri. eurodac 1996: 382-387 [doi]

System design using an integrated specification and performance modeling methodologyAmbar Sarkar. eurodac 1996: 542-547 [doi]

Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionalityClaus Schneider, Wolfgang Ecker. eurodac 1996: 509-514 [doi]

Object-oriented hardware modelling - where to apply and what are the objects?Guido Schumacher, Wolfgang Nebel. eurodac 1996: 428-433 [doi]

A system level HW/SW partitioning and optimization toolMarkus Schwiegershausen, Holger Kropp, Peter Pirsch. eurodac 1996: 120-125 [doi]

Software methodologies for VHDL code static analysis based on flow graphsDonatella Sciuto, Luciano Baresi, Cristiana Bolchini. eurodac 1996: 406-411 [doi]

A system for compiling and debugging structured data processing controllersAndrew Seawright, Joseph Buck, Ulrich Holtmann, Wolfgang Meyer, Barry M. Pangrle, Rob Verbrugghe. eurodac 1996: 86-91 [doi]

A practical clock router that accounts for the capacitance derived from parallel and cross segmentsMitsuho Seki, Kazuo Kato, S. Kobayashi, Kouki Tsurusaki. eurodac 1996: 362-367 [doi]

Power analysis for sequential circuits at logic levelMatthias A. Senn, Peter H. Schneider, Bernd Wurth. eurodac 1996: 22-27 [doi]

Automatic workflow generationVladimir A. Shepelev, Stephen W. Director. eurodac 1996: 104-109 [doi]

Entity overloading for mixed-signal abstraction in VHDLC.-J. Richard Shi. eurodac 1996: 562-567 [doi]

Hierarchical behavioral partitioning for multicomponent synthesisVinoo Srinivasan, Nand Kumar, Ranga Vemuri. eurodac 1996: 212-217 [doi]

Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996Graham Symonds, Wolfgang Nebel, editors, IEEE Computer Society Press, 1996. [doi]

Simulation and design optimization of microsystems based on standard simulators and adaptive search techniquesWolfgang Süß, Horst Eggert, M. Georges-Schleuter, Wilfried Jakob, S. Meinzer, Alexander Quinte. eurodac 1996: 322-327 [doi]

An approach for integrated specification and design of real-time systemsYankin Tanurhan, H. Gölz, Stefan Schmerler, Klaus D. Müller-Glaser. eurodac 1996: 258-263 [doi]

VHDL fault simulation for defect-oriented test and diagnosis of digital ICsJoão Paulo Teixeira, F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos. eurodac 1996: 450-455 [doi]

CoWare - a design environment for heterogenous hardware/software systemsKarl van Rompaey, Ivo Bolsens, Hugo De Man, Diederik Verkest. eurodac 1996: 252-257 [doi]

Mapping statechart models onto an FPGA-based ASIP architectureChristian Veith, Klaus Buchenrieder, Andreas Pyttel. eurodac 1996: 184-189 [doi]

Automatic diagnosis may replace simulation for correcting simple design errorsAyman M. Wahba, Dominique Borrione. eurodac 1996: 476-481 [doi]

A new concept for accurate modeling of VLSI interconnections and its application for timing simulationBernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser. eurodac 1996: 72-77 [doi]

Automatic synthesis of extended burst-mode circuits using generalized C-elementsKenneth Y. Yun. eurodac 1996: 290-295 [doi]

1995

Proceedings EURO-DAC 95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995IEEE Computer Society, 1995.

Generating several solutions for the scheduling problem in high-level synthesisHans Achatz. eurodac 1995: 66-71 [doi]

Functional-level analog macromodeling with piecewise linear signalsJerzy Dabrowski. eurodac 1995: 222-227 [doi]

An improved relaxation approach for mixed system analysis with several simulation toolsVladimir B. Dmitriev-Zdorov, Bernhard Klaassen. eurodac 1995: 274-279 [doi]

Mesh current method for computing the current distribution in planar conductor surfaces and possible applications in circuit simulationArmin Englmaier. eurodac 1995: 348-353 [doi]

An approach to guided incremental specificationThomas Gabler, Sabine März-Rössel. eurodac 1995: 368-373 [doi]

A formal non-heuristic ATPG approachManfred Henftling, Hannes C. Wittmann, Kurt Antreich. eurodac 1995: 248-253 [doi]

Prediction of radiated electromagnetic emissions from PCB traces based on green dyadicsE. Leroux, Flavio G. Canavero, G. Vecchi. eurodac 1995: 354-359 [doi]

VHDL quality: synthesizability, complexity and efficiency evaluationM. Mastretti. eurodac 1995: 482-487 [doi]

Generating VHDL-A—like models using ABSynthVincent Moser, Hans Peter Amann, Pascal Nussbaum, Fausto Pellandini. eurodac 1995: 522-527 [doi]

Timing optimization by bit-level arithmetic transformationsLuc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man. eurodac 1995: 48-53 [doi]

Latest benchmark results of VHDL simulation systemsEugen Röhm. eurodac 1995: 406-411 [doi]

LibQA—library quality assurance for VHDL synthesis and simulationRonald B. Stewart. eurodac 1995: 516-521 [doi]

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