Journal: IEEE Design & Test of Computers

Volume 16, Issue 4

1 -- 0Yervant Zorian. Integration Continues
5 -- 6. News
6 -- 0. Letter to the Editor
7 -- 13Terry Thomas. Technology for IP Reuse and Portability
14 -- 15Charles F. Hawkins, Jerry M. Soden. Deep Submicron CMOS Current IC Testing: Is There a Future?
16 -- 17Bernard Courtois, R. D. (Shawn) Blanton. Guest Editors Introduction
18 -- 27Tamal Mukherjee, Gary K. Fedder, R. D. (Shawn) Blanton. Hierarchical Design and Test of Integrated Microsystems
28 -- 38Salvador Mir, Benoît Charlot. On the Integration of Design and Test for Chips Embedding MEMS
39 -- 47Nicholas R. Swart. A Design Flow for Micromachined Electromechanical Systems
48 -- 56Alain Béliveau, Guy T. Spencer, Keith A. Thomas, Scott L. Roberson. Evaluation of MEMS Capacitive Accelerometers
58 -- 65Edward K. Chan, Krishna Garikipati, Robert W. Dutton. Comprehensive Static Characterization of Vertical Electrostatically Actuated Polysilicon Beams
66 -- 73Charles F. Hawkins, Jaume Segura, Jerry M. Soden, Ted Dellin. Test and Reliability: Partners in IC Manufacturing, Part 2
74 -- 83Peter J. Ashenden, Philip A. Wilsey. Protected Shared Variables in VHDL: IEEE Standard 1076a
84 -- 88Ralph Mason, Shing Ma. Analog DFT Using an Undersampling Technique
90 -- 95. A D&T Roundtable: Design Automation in Europe
96 -- 99Dilip K. Bhavsar. ITC 99 Panels
100 -- 101. Conference Reports
102 -- 108. IEEE Design & Test of Computers 1999 Annual Index, Volume 16
109 -- 0. DATC Newsletter
110 -- 111. TTTC Newsletter
112 -- 0Chris Rowen. Sailing on a Sea of Processors

Volume 16, Issue 3

6 -- 7Yervant Zorian. D&T Expands
8 -- 10. News
8 -- 0. Letter to the Editor
11 -- 19Hugo De Man. System-on-Chip Design: Impact on Education and Research
20 -- 22Tony Ambler, Ben Bennetts. Guest Editors Introduction: Test and the Product Life Cycle
23 -- 27Jon Turino. Design for Test and Time to Market: A Personal Perspective
34 -- 43Mike Wondolowski, Ben Bennetts, Adam W. Ley. Boundary Scan: The Internet of Test
44 -- 52Bertram Weber. Automating PBX System Testing
53 -- 63Susana Stoica. Generating Functional Design Verification Tests
64 -- 71Charles F. Hawkins, Jaume Segura. Test and Reliability: Partners in IC Manufacturing, Part 1
72 -- 80Mark C. Hansen, Hakan Yalcin, John P. Hayes. Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
81 -- 89Andreas Steininger, Christopher Temple. Economic Online Self-Test in the Time-Triggered Architecture
90 -- 101Michael Nicolaidis, Ricardo de Oliveira Duarte. Fault-Secure Parity Prediction Booth Multipliers
102 -- 111Lee Melatti, Barry Blancha. Testing Methodology for FireWire
121 -- 122Mukund Modi. Status Report on Standards Affecting Design and Test
128 -- 0Stephen K. Sunter. Analog, digital, and mixed-signal people

Volume 16, Issue 2

0 -- 93. Conference Reports
5 -- 0Mukund Modi. Mixed-Signal Test Bus, Embedded Core Test Efforts Advance
8 -- 14. Gordon E. Moore: A Pioneer Looks Back at Semiconductors
15 -- 16Vijay K. Madisetti. Guest Editor s Introduction: Reengineering Digital Systems
17 -- 25Ronald C. Stogdill. Dealing with Obsolete Parts
26 -- 37Gregory H. Chisholm, Steven T. Eckmann, Christopher M. Lain, Robert Veroff. Understanding Integrated Circuits
38 -- 47Vijay K. Madisetti, Yong-Kyu Jung, Moinul H. Khan, Jeongwook Kim, Theodore Finnessy. Reengineering Legacy Embedded Systems
48 -- 56Rao R. Tummala, Vijay K. Madisetti. System on Chip or System on Package?
58 -- 65Manoj Sachdev, Hans G. Kerkhoff. Configurations for IDDQ-Testable PLAs
66 -- 73Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi. Design Verification of FPGA Implementations
74 -- 83Alireza Kaviani, Stephen Dean Brown. The Hybrid Field-Programmable Architecture
84 -- 91. IC Reliability and Test: What Will Deep Submicron Bring?
94 -- 95. Test Technology TC Newsletter
96 -- 0Scott Davidson. How Do I Boot Thee? Let Me Check Page 3

Volume 16, Issue 1

1 -- 0Yervant Zorian. Focus on DRAMs
3 -- 4. News
5 -- 0. Conference Reports
6 -- 0. Panel Summaries
9 -- 15. Dado Banatao: Profile of a Silicon Valley Entrepreneur
16 -- 18Robin Saxby, Peter Harrod. Test in the Emerging Intellectual Property Business
19 -- 21Bruce F. Cockburn, Fabrizio Lombardi, Fred J. Meyer. Guest Editors Introduction: DRAM Architecture and Testing
22 -- 31Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott. Fault Models and Tests for a 2-Bit-per-Cell MLDRAM
32 -- 41Duncan G. Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie. Computational RAM: Implementing Processors in Memory
42 -- 52Bruce Millar, Peter Gillingham. Two High-Bandwidth Memory Bus Structures
53 -- 58Shinji Miyano, Katsuhiko Sato, Kenji Numata. Universal Test Interface for Embedded-DRAM Testing
59 -- 70Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang. A Programmable BIST Core for Embedded DRAM
71 -- 79Kenneth M. Butler. Estimating the Economic Benefits of DFT
88 -- 89Mukund Modi. P1532, WAVES, and a New Initiative
96 -- 0Al Crouch. The DFT Psychic Network