Journal: IEEE Design & Test of Computers

Volume 23, Issue 6

434 -- 0Tim Cheng. Handling variations and uncertainties
436 -- 437T. M. Mak, Sani R. Nassif. Guest Editors Introduction: Process Variation and Stochastic Design and Test
438 -- 451Mehrdad Nourani, Arun Radhakrishnan. Testing On-Die Process Variation in Nanometer VLSI
452 -- 462Sounil Biswas, Ronald D. Blanton. Statistical Test Compaction Using Binary Decision Trees
464 -- 475Soumendu Bhattacharya, Abhijit Chatterjee. A DFT Approach for Testing Embedded Systems Using DC Sensors
476 -- 483Eric S. Fetzer. Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design
484 -- 490Dennis Sylvester, David Blaauw, Eric Karl. ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
500 -- 501Grant Martin. Book Reviews: NoC, NoC ... Who s there?
502 -- 503Fabian Vargas. Design and test on chip for EMC
504 -- 505Vladimir Hahanov. East-West Design & Test Workshop
507 -- 0Bruce C. Kim. TTTC Newsletter
520 -- 0Shekhar Borkar. Tackling variability and reliability challenges

Volume 23, Issue 5

333 -- 0Kwang-Ting (Tim) Cheng. The New World of ESL Design
335 -- 337Sandeep K. Shukla, Carl Pixley, Gary Smith. Guest Editors Introduction: The True State of the Art of ESL Design
338 -- 347Patrick Schaumont, Ingrid Verbauwhede. A Component-Based Design Environment for ESL Design
348 -- 358Ivan Radojevic, Zoran A. Salcic, Partha S. Roop. Modeling Embedded Systems: From SystemC and Esterel to DFCharts
359 -- 374Douglas Densmore, Roberto Passerone. A Platform-Based Taxonomy for ESL Design
375 -- 386Stephen A. Edwards. The Challenges of Synthesizing Hardware from C-Like Languages
387 -- 0John Sanguinetti. A Different View: Hardware Synthesis from SystemC is a Maturing Technology
388 -- 389Kenneth M. Butler. Guest Editor s Introduction: ITC Helps Get More Out of Test
390 -- 400Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer. Extracting Defect Density and Size Distributions from Product ICs
402 -- 412Nisar Ahmed, Mohammad Tehranipoor. Improving Transition Delay Test Using a Hybrid Method
414 -- 424Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura. Impact of Thermal Gradients on Clock Skew and Testing
425 -- 0Bruce C. Kim. Test Technology TC Newsletter
426 -- 427Scott Davidson. Book Reviews: A Comprehensive EDA Handbook
428 -- 429Victor Berman. Standards: DASC sees moves toward formality in design
430 -- 431. CEDA Currents
432 -- 0Anne E. Gattiker. Getting More out of ITC

Volume 23, Issue 4

261 -- 0Kwang-Ting (Tim) Cheng. Vision from the Top
262 -- 265Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar. Conference Reports
268 -- 277Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio. On-Chip Testing Techniques for RF Wireless Transceivers
278 -- 293Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel. Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
294 -- 303Nur A. Touba. Survey of Test Vector Compression Techniques
304 -- 310Walden C. Rhines. Sociology of Design and EDA
315 -- 0Ajay Khoche. Panel Summaries: Real-Time Volume Diagnostics--Requirements and Challenges
316 -- 317Victor Berman. Standards: The P1685 IP-XACT IP Metadata Standard
318 -- 319Sachin S. Sapatnekar. Book Reviews: Plumbing the Depths of Leakage
320 -- 323Bruce C. Kim. Test Technology TC Newsletter
322 -- 325. CEDA Currents
328 -- 0Scott Davidson. Who Reads This Stuff Anyway?

Volume 23, Issue 3

181 -- 0Kwang-Ting (Tim) Cheng. The Need for a SiP Design and Test Infrastructure
182 -- 184Sachin S. Sapatnekar, Grant Martin. DAC Highlights
185 -- 0Fabian Vargas. 2006 Latin American Test Workshop
186 -- 187Bruce C. Kim, Yervant Zorian. Guest Editors Introduction: Big Innovations in Small Packages
188 -- 195Peter Rickert, William Krenik. Cell Phone Integration: SiP, SoC, and PoP
196 -- 202Thomas Brandtner. Chip-Package Codesign Flow for Mixed-Signal SiP Designs
203 -- 211Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda. System-in-Package Testing: Problems and Solutions
212 -- 219Dong Gun Kam, Joungho Kim, Jiheon Yu, Ho Choi, Kicheol Bae, Choonheung Lee. Packaging a 40-Gbps Serial Link Using a Wire-Bonded Plastic Ball Grid Array
220 -- 233Vijay K. Madisetti. Electronic System, Platform, and Package Codesign
234 -- 243Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell. A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs
248 -- 249Grant Martin. The First Transaction, but not the Last
250 -- 0Bruce C. Kim. Test Technology Technical Council Newsletter
252 -- 253. CEDA Currents
256 -- 0T. M. Mak. Is System in Package the Panacea for Integration?

Volume 23, Issue 2

85 -- 0Kwang-Ting (Tim) Cheng. Dealing with early life failures
86 -- 87Phil Nigh. Guest Editor s Introduction: Evolving Methods for Detecting and Handling Reliability Defects
88 -- 98Mohd Fairuz Zakaria, Zainal Abu Kassim, Melanie Po-Leen Ooi, Serge N. Demidenko. Reducing Burn-in Time through High-Voltage Stress Test and Weibull Statistical Analysis
100 -- 109Ritesh P. Turakhia, W. Robert Daasch, Joel Lurkins, Brady Benware. Changing Test and Data Modeling Requirements for Screening Latent Defects as Statistical Outliers
110 -- 116Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh. Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction
118 -- 126John M. Carulli Jr., Thomas J. Anderson. The Impact of Multiple Failure Modes on Estimating Product Field Reliability
128 -- 136Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng. Test Consideration for Nanometer-Scale CMOS Circuits
138 -- 146Selahattin Sayil. Optical Contactless Probing: An All-Silicon, Fully Optical Approach
148 -- 158Jérôme Chevalier, Maxime de Nanclas, Luc Filion, Olivier Benny, Mathieu Rondonneau, Guy Bois, El Mostapha Aboulhamid. A SystemC Refinement Methodology for Embedded Software
160 -- 161Brian Bailey. Was it worth the wait? Yes!
162 -- 163Scott Davidson. An insider s look at microprocessor design
164 -- 166Carol Stolicny. ITC 2005 panels
167 -- 0Sandip Kundu. TTTC technical forum honoring Sudhakar M. Reddy
168 -- 171Kartikeya Mayaram. CEDA Currents
175 -- 0. TTTC Newsletter
176 -- 0Burnell West. Making more out of open-source tools

Volume 23, Issue 1

5 -- 6Kwang-Ting Cheng. New beginnings, continued success
8 -- 19Bernhard Peischl, Franz Wotawa. Automated Source-Level Error Localization in Hardware Designs
20 -- 29Hamilton Klimach, Carlos Galup-Montoro, Márcio C. Schneider, Alfredo Arnaud. MOSFET Mismatch Modeling: A New Approach
30 -- 37Kevin Lucas, Chi-Min Yuan, Robert Boone, Karl Wimmer, Kirk Strozewski, Olivier Toublan. Logic Design for Printability Using OPC Methods
38 -- 45Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante. Early, Accurate Dependability Analysis of CAN-Based Networked Systems
46 -- 57David C. Keezer, Dany Minier, Patrice Ducharme. Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses
58 -- 66Antonio Petraglia, Jorge M. Cañive, Mariane R. Petraglia. Efficient Parametric Fault Detection in Switched-Capacitor Filters
67 -- 68Scott Davidson. Searching for clues: Diagnosing IC failures
69 -- 70Christopher Songer. Embedded systems and the kitchen sink
71 -- 0Ken Butler. Conference Reports: 2005 International Test Conference
80 -- 0Scott Davidson. All about getting it