External Links

    Journal: IEEE Design & Test of Computers

    Volume 3, Issue 6

    13 -- 25Hugo De Man, Jan M. Rabaey, Paul Six, Luc J. M. Claesen. Cathedral-II: A Silicon Compiler for Digital Signal Processing
    26 -- 32Frans P. M. Beenker, Karel J. E. van Eerdewijk, Robert B. W. Gerritsen, Frank N. Peacock, Max Van der Star. Macro Testing: Unifying IC and Board Test
    35 -- 41Joachim Mucha, Wilfried Daehn, Josef Gross. Self-Test in a Standard Cell Environment

    Volume 3, Issue 5

    11 -- 15Kenneth P. Parker. Testability: Barriers to Acceptance
    17 -- 26Madhukar K. Reddy, Sudhakar M. Reddy. Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops
    27 -- 37Sunil K. Jain, Charles E. Stroud. Built-in Self Testing of Embedded Memories
    39 -- 48E. Ted Grinthal. Software Quality Assurance And CAD User Interfaces
    49 -- 56David Hightower, Aart J. de Geus, Patrick Fasang, Robert Griffin, Gary Leive. Computer-Aided-Design Research at the GE Microelectronics Center

    Volume 3, Issue 4

    15 -- 22Thirumalai Sridhar. A New Parallel Test Approach for Large Memories
    23 -- 29Teruo Tamama, Norio Kuji. Integrating an Electron-Beam System into VLSI Fault Diagnosis
    33 -- 42Dennis Petrich. Achieving Accurate Timing Measurements on TTL/CMOS Devices
    43 -- 54Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller. SMART and FAST: Test Generation for VLSI Scan-Design Circuits
    56 -- 64Jerry M. Soden, Charles F. Hawkins. Test Considerations for Gate Oxide Shorts in CMOS ICs
    72 -- 0J. Daniel Nash. New Products Design
    73 -- 75Conrad Zagwyn. New Products Test
    76 -- 77Robert E. Anderson. Book Reviews

    Volume 3, Issue 3

    18 -- 24Dave W. Palmer, John A. Wisniewski. IC Design Capability Conversion from Mainframe to Workstation Environment
    25 -- 30Mark A. Linton. Benchmarking Engineering Workstations
    31 -- 37Rolf-Dieter Fiebrich. A Supercomputer Workstation for VLSI CAD
    38 -- 45Akira Sugimoto. VEGA: A Visual Modeling Language for Digital Systems
    46 -- 51K. L. Kodandapani, Edward J. McGrath. A Wirelist Compare Program for Verifying VLSI Layouts
    52 -- 56Dilip K. Bhavsar. A New Economical Implementation for Scannable Flip-Flops in MOS
    65 -- 67J. Daniel Nash. New Products Design
    68 -- 69Conrad Zagwyn. New Products Test

    Volume 3, Issue 2

    12 -- 16Allen Dewey, Anthony Gadient. VHDL Motivation
    17 -- 27James H. Aylor, Ronald Waxman, Charles Scarratt. VHDL - Feature Description and Analysis
    28 -- 41Roger Lipsett, Erich Marschner, Moe Shahdad. VHDL - The Language
    42 -- 47Alfred S. Gilman. VHDL - The Designer Environment
    48 -- 53Al Lowenstein, Greg Winter. VHDL's Impact on Test
    54 -- 65J. D. Nash, Larry F. Saunders. VHDL Critique
    66 -- 73William R. Simpson, Carol J. Dowling. WRAPLE: The Weighted Repair Assistance Program Learning Extension
    84 -- 0J. Daniel Nash. New Products Design
    85 -- 0Conrad Zagwyn. New Products Test

    Volume 3, Issue 1

    12 -- 23Rostam Joobbani, Daniel P. Siewiorek. WEAVER: A Knowledge-Based Routing Expert
    24 -- 34Walter S. Scott, John K. Ousterhout. Magic's Circuit Extractor
    35 -- 44Andrzej J. Strojwas. The CMU-CAM System
    45 -- 57Hingsum S. Fung, Sanford S. Hirschhorn. An Automatic DFT System for the Silc Silicon Compiler
    58 -- 65Anshul Kumar, Anjali Arya, V. V. Swaminathan, Amit Misra. Automatic Generation of Digital System Schematic Diagrams
    66 -- 74Louis K. Scheffer, Ronny Soetarman. Hierarchical Analysis of IC Artwork with User-Defined Rules
    75 -- 81C. Durward Rogers. The VIVID Symbolic Design System: Current Overview And Future Directions
    88 -- 90Conrad Zagwyn. New Products Test
    91 -- 92J. Daniel Nash. New Products Design
    95 -- 0Robert E. Anderson. Book Reviews
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