External Links

    Journal: IEEE Design & Test of Computers

    Volume 5, Issue 6

    8 -- 13Ronald A. Rohrer. Evolution of the electronic design automation industry
    14 -- 21Tsuneta Sudo. Design automation systems in Japan
    22 -- 32Charles E. Stroud. Automated BIST for sequential logic synthesis
    33 -- 42Derek L. Beatty, Randal E. Bryant. Incremental switch-level analysis
    44 -- 56Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu. PROUD: a sea-of-gates placement algorithm
    57 -- 67Leendert M. Huisman. The reliability of approximate testability measures

    Volume 5, Issue 5

    9 -- 27Kenneth D. Wagner. Clock system design
    28 -- 40Atsushi Kara, Ravi Rastogi, Kazuhiko Kawamura. An expert system to automate timing design
    41 -- 59Xi-an Zhu, Melvin A. Breuer. A knowledge-based system for selecting test methodologies
    60 -- 79Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya. Test research in Japan

    Volume 5, Issue 4

    14 -- 28Xi-an Zhu, Melvin A. Breuer. Analysis of testable PLA designs
    29 -- 36Paul H. Bardell, William H. McAnney. Built-in test for RAMs
    38 -- 48Eduard Cerny, El Mostapha Aboulhamid, Guy Bois, Jocelyn Cloutier. Built-in self-test of a CMOS ALU

    Volume 5, Issue 3

    11 -- 21Peter M. Maurer. Design verification of the WE 32106 math accelerator unit
    22 -- 30Charles E. Stroud, Ronald R. Munoz, David A. Pierce. Behavioral model synthesis with Cones
    31 -- 42Sumit Ghosh. Behavioral-level fault simulation
    43 -- 55Tom E. Kirkland, M. Ray Mercer. Algorithms for automatic test pattern generation
    56 -- 63Robert J. Powers. Throughput advantages of asynchronous prober control

    Volume 5, Issue 2

    8 -- 15Vishwani D. Agrawal, Kwang-Ting Cheng, Daniel D. Johnson 0004, Tonysheng Lin. Designing circuits with partial scan
    16 -- 23Ed O. Schlotzhauer. Real-world board test effectiveness
    24 -- 35Algirdas J. Gruodis, Dale E. Hoffman. 250-MHz advanced test systems
    36 -- 47Duane S. Boning, Dimitri A. Antoniadis. A workstation approach to IC process and device design

    Volume 5, Issue 1

    8 -- 18J. R. Armstrong. Chip-level modeling with HDLs
    19 -- 29Chad L. Mitchell, Michael J. Flynn. A workbench for computer architects
    30 -- 42Sumit Ghosh. Using Ada as an HDL
    43 -- 47Joshua S. L. Wong, David W. Y. Kwok. A single-row transformation technique
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