| 385 | -- | 0 | Kunio Uchiyama. Foreword |
| 386 | -- | 393 | Koji Kai, Minoru Fujishima. Prospective Silicon Applications and Technologies in 2025 |
| 394 | -- | 400 | Toru Shimizu, Kazutami Arimoto, Osamu Nishii, Sugako Otani, Hiroyuki Kondo. Low Power Platform for Embedded Processor LSIs |
| 401 | -- | 410 | Tianruo Zhang, Chen Liu, Minghui Wang, Satoshi Goto. Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining |
| 411 | -- | 418 | Yibo Fan, Xiaoyang Zeng, Satoshi Goto. Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC |
| 419 | -- | 427 | Gang He, Dajiang Zhou, Jinjia Zhou, Tianruo Zhang, Satoshi Goto. A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder |
| 428 | -- | 438 | Yiqing Huang, Xiaocong Jin, Jin Zhou, Jia Su, Takeshi Ikenaga. Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k×4k@60 fps |
| 439 | -- | 447 | Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto. Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder |
| 448 | -- | 457 | Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi, Masahiko Yoshimoto. A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition |
| 458 | -- | 467 | Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi, Masahiko Yoshimoto. VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition |
| 468 | -- | 476 | Xi Zhang, Chongmin Li, Zhenyu Liu, Haixia Wang, Dongsheng Wang, Takeshi Ikenaga. A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction |
| 477 | -- | 486 | Makoto Sugihara. A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors |
| 487 | -- | 494 | Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada. All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter |
| 495 | -- | 503 | Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata. A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits |
| 504 | -- | 510 | Zhihua Gui, Fan Yang, Xuan Zeng. Stochastic Non-homogeneous Arnoldi Method for Analysis of On-Chip Power Grid Networks under Process Variations |
| 511 | -- | 519 | Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada. On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch |
| 520 | -- | 529 | Yuji Kunitake, Toshinori Sato, Hiroto Yasuura. Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI |
| 530 | -- | 538 | Tadayoshi Enomoto, Nobuaki Kobayashi. A Large Read and Write Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM |
| 539 | -- | 547 | Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi. Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell ::::V::::::TH:: Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs) |
| 548 | -- | 556 | Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi. A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells |
| 557 | -- | 566 | Yoshimitsu Takamatsu, Ryuichi Fujimoto, Tsuyoshi Sekine, Takaya Yasuda, Mitsumasa Nakamura, Takuya Hirakawa, Masato Ishii, Motohiko Hayashi, Hiroya Ito, Yoko Wada, Teruo Imayama, Tatsuro Oomoto, Yosuke Ogasawara, Masaki Nishikawa, Yoshihiro Yoshida, Kenji Yoshioka, Shigehito Saigusa, Hiroshi Yoshida, Nobuyuki Itoh. A Single-Chip RF Tuner/OFDM Demodulator for Mobile Digital TV Application |
| 567 | -- | 574 | Mohiuddin Hafiz, Nobuo Sasaki, Takamaro Kikkawa. A 500 Mb/s Differential Input Non-coherent BPSK Receiver for UWB-IR Communication |
| 575 | -- | 581 | Jiangtao Sun, Qing Liu, Yong-Ju Suh, Takayuki Shibata, Toshihiko Yoshimasu. A 66-dBc Fundamental Suppression Frequency Doubler IC for UWB Sensor Applications |
| 582 | -- | 588 | Hiroaki Katsurai, Hideki Kamitsuna, Hiroshi Koizumi, Jun Terada, Yusuke Ohtomo, Tsugumichi Shibata. An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System |
| 589 | -- | 597 | Ryuichi Fujimoto, Kyoya Takano, Mizuki Motoyoshi, Uroschanit Yodprasit, Minoru Fujishima. Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100 GHz |
| 598 | -- | 604 | Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai. 0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications |
| 605 | -- | 612 | Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara. An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic |
| 613 | -- | 618 | Koichi Yamaguchi, Masayuki Mizuno. Dicode Partial Response Signaling over Inductively-Coupled Channel |
| 619 | -- | 626 | Koichi Yamaguchi, Masayuki Mizuno. A Duobinary Signaling for Asymmetric Multi-Chip Communication |
| 627 | -- | 634 | Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada. A 0.18-µm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability |
| 635 | -- | 640 | Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei. A 500 MS/s 600 µW 300 µm:::2::: Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process |
| 641 | -- | 647 | Fatemeh Abrishamian, Katsumi Morishita. Broadening Adjustable Range on Post-Fabrication Resonance Wavelength Trimming of Long-Period Fiber Gratings and the Mechanisms of Resonance Wavelength Shifts |
| 648 | -- | 653 | Yan-Ru Tseng, Tzuen-Hsi Huang, Shang-Hsun Wu. A 7-GHz, Low-Power, Low Phase-Noise Differential Current-Reused VCO Utilizing a Trifilar-Transformer-Feedback Technique |
| 654 | -- | 662 | Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. Cascaded Time Difference Amplifier with Differential Logic Delay Cell |
| 663 | -- | 669 | Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima. A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core |
| 670 | -- | 673 | Guo-Ming Sung, Ying-Tsu Lai, Chien-Lin Lu. A Resistor-Compensation Technique for CMOS Bandgap and Current Reference with Simplified Start-Up Circuit |