| 413 | -- | 0 | Masahiko Yoshimoto. Foreword |
| 414 | -- | 420 | Kiyoshi Takeuchi. Impact of Discrete-Charge-Induced Variability on Scaled MOS Devices |
| 421 | -- | 431 | Shiro Dosho. Digital Calibration and Correction Methods for CMOS Analog-to-Digital Converters |
| 432 | -- | 440 | Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma. An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures |
| 441 | -- | 446 | Weiwei Shen, Yibo Fan, Xiaoyang Zeng. A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K × 2 K Applications |
| 447 | -- | 455 | Yibo Fan, Jialiang Liu, Dexue Zhang, Xiaoyang Zeng, Xinhua Chen. An 8 × 4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4 K × 2 K H.264/AVC Encoder |
| 456 | -- | 467 | Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi. A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition |
| 468 | -- | 477 | Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino. High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications |
| 478 | -- | 486 | Changsheng Zhou, Yuebin Huang, Shuangqu Huang, Yun Chen, Xiaoyang Zeng. An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution |
| 487 | -- | 494 | Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring |
| 495 | -- | 505 | Shouyi Yin, Yang Hu, Zhen Zhang, Leibo Liu, Shaojun Wei. Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC |
| 506 | -- | 515 | Naohiro Hamada, Hiroshi Saito. Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation |
| 516 | -- | 522 | Jung-Lin Yang, Shin-Nung Lu, Pei-Hsuan Yu. Asynchronous Circuit Design on Field Programmable Gate Array Devices |
| 523 | -- | 533 | Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto. A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing |
| 534 | -- | 545 | Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto. Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips |
| 546 | -- | 554 | Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada. Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling |
| 555 | -- | 563 | Akira Kotabe, Kiyoo Itoh, Riichiro Takemura. 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs |
| 564 | -- | 571 | Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi. Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor |
| 572 | -- | 578 | Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto. A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme |
| 579 | -- | 585 | Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi. A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme |
| 586 | -- | 593 | Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata. Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation |
| 594 | -- | 599 | Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh. Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays |
| 600 | -- | 608 | Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh. t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing |
| 609 | -- | 616 | Kousuke Miyaji, Ryoji Yajima, Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai, Ken Takeuchi. Initialize and Weak-Program Erasing Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive |
| 617 | -- | 626 | Hyoungjun Na, Tetsuo Endoh. Current Controlled MOS Current Mode Logic with Auto-Detection of Threshold Voltage Fluctuation |
| 627 | -- | 634 | Tetsuya Iizuka, Kunihiro Asada. All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator |
| 635 | -- | 642 | Hiroki Yabe, Makoto Ikeda. 3-D Range Map Acquisition System Based on CMOS Image Sensor Using Time-Multiplexing Structured Pattern |
| 643 | -- | 650 | Jinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada. On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction |
| 651 | -- | 660 | Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara. Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device |
| 661 | -- | 667 | Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada. A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology |
| 668 | -- | 676 | Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda. 2 Wireless Power Transmission for Non-contact Wafer-Level Testing |
| 677 | -- | 685 | Toru Sai, Yasuhiro Sugimoto. A Current-Mode Buck DC-DC Converter with Frequency Characteristics Independent of Input and Output Voltages Using a Quadratic Compensation Slope |
| 686 | -- | 695 | Shin-ichi O'Uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara. A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology |
| 696 | -- | 705 | Bo Liu, Bo Yang 0004, Shigetoshi Nakatake. Layout-Aware Variability Characterization of CMOS Current Sources |
| 706 | -- | 709 | Amir Fathi, Sarkis Azizian, Khayrollah Hadidi, Abdollah Khoei. Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations |
| 710 | -- | 712 | Amir Fathi, Sarkis Azizian, Khayrollah Hadidi, Abdollah Khoei. A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations |
| 713 | -- | 716 | Shoichi Oshima, Mamoru Ugajin, Mitsuru Harada. Third-Harmonic Envelope Feedback Method for High-Efficiency Linear Power Amplifiers |
| 717 | -- | 724 | Michinari Shimoda, Toyonori Matsuda, Kazunori Matsuo, Yoshitada Iyama. Estimation of Surface Waves along a Metal Grating Using an Equivalent Impedance Model |
| 725 | -- | 732 | Jun Shibayama, Keisuke Watanabe, Ryoji Ando, Junji Yamauchi, Hisamatsu Nakano. Frequency-Dependent Formulations of a Drude-Critical Points Model for Explicit and Implicit FDTD Methods Using the Trapezoidal RC Technique |
| 733 | -- | 743 | Alexander Edward, Pak Kwong Chan. An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18 µm CMOS |
| 744 | -- | 751 | Mohammad Reza Reshadinezhad, Mohammad Hossein Moaiyeri, Keivan Navi. An Energy-Efficient Full Adder Cell Using CNFET Technology |
| 752 | -- | 760 | Hideo Sakai, Shin-ichi O'Uchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara, Hiroki Ishikuro. High-Frequency Precise Characterization of Intrinsic FinFET Channel |
| 761 | -- | 764 | Yu Sugita, Yoshifumi Takasaki, Keiji Kuroda, Yuzo Yoshikuni. Transverse Characteristics of Two-Dimensional Imaging by Fourier Domain Optical Coherence Tomography |
| 765 | -- | 767 | Zhisheng Li, Johan Bauwelinck, Guy Torfs, Xin Yin, Jan Vandewege. A New Common-Mode Stabilization Method for a CMOS Cascode Class-E Power Amplifier with Driver Stage |