Journal: IEEE Transactions on Computers

Volume 32, Issue 9

785 -- 798Witold S. Wojciechowski, Anthony S. Wojcik. Automated Design of Multiple-Valued Logic Circuits by Automatic Theorem Proving Techniques
799 -- 808Timothy C. K. Chou, Jacob A. Abraham. Load Redistribution Under Failure in Distributed Systems
809 -- 825Thomas F. Schwab, Stephen S. Yau. An Algebraic Model of Fault-Masking Logic Circuits
826 -- 830Quentin F. Stout. Mesh-Connected Computers with Broadcasting
831 -- 844James E. Smith, Paklin Lam. A Theory of Totally Self-Checking System Design
845 -- 858Inder S. Gopal, Don Coppersmith, C. K. Wong. Optimal Wiring of Movable Terminals
859 -- 861Makoto Kobayashi. Dynamic Profile of Instruction Sequences for the IBM System/370
861 -- 863Leslie G. Valiant. Optimality of a Two-Phase Strategy for Routing in Interconnection Networks
863 -- 868Chamarty D. V. P. Rao, Nripendra N. Biswas. On the Minimization of Wordwidth in the Control Memory of a Microprogrammed Digital Computer
868 -- 872Martin de Prycker. Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model
872 -- 874Murali R. Varanasi, T. R. N. Rao, Son Pham. Memory Package Error Detection and Correction
874 -- 877Trieu-Kien Truong, Irving S. Reed, C.-S. Yeh, Howard M. Shao. A Parallel Architecture for Digital Filtering Using Fermat Number Transforms
878 -- 880R. Gnanasekaran. On a Bit-Serial Input and Bit-Serial Output Multiplier

Volume 32, Issue 8

697 -- 707Bernard Chazelle. The Bottom-Left Bin-Packing Heuristic: An Efficient Implementation
707 -- 716Tomás Lang, Mateo Valero, Miguel Angel Fiol. Reduction of Connections for Multibus Organization
717 -- 726Shuji Tasaka. Stability and Performance of the R-ALOHA Packet Broadcast System
727 -- 730John J. Metzner. A Parity Structure for Large Remotely Located Replicated Data Files
731 -- 744Neil Weste, David J. Burr, Bryan D. Ackland. Dynamic Time Warp Pattern Matching Using an Integrated Multiprocessing Array
745 -- 747Nuno Bandeira, Ken Vaccaro, James A. Howard. A Two s Complement Array Multiplier Using True Values of the Operands
748 -- 750Ranjan Chaudhuri, Son Pham, Oscar N. Garcia. Solution of an Open Problem on Probabilistic Grammars
750 -- 754Gian Carlo Bongiovanni. Two VLSI Structures for the Discrete Fourier Transform
754 -- 760Sharad C. Seth, Lester Lipsky. A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems
760 -- 763Werner Bux. Analysis of a Local-Area Bus System with Controlled Access
763 -- 766Wesley W. Chu, Wilhelm Haller, Kin K. Leung. Reservation Channel Access Protocol for High Speed Local Networks with Star Configurations
766 -- 770P. V. Afshari, Steven C. Bruell, Richard Y. Kain. On the Load Balancing Bus Accessing Scheme
770 -- 774Curtis Abbott. A Symbolic Simulator for Microprogram Development
774 -- 777A. F. Bashir, V. Susarla, K. Vairavan. A Statistical Study of the Performance of a Task Scheduling Algorithm
777 -- 782. Greedy Diagnosis of Hybrid Fault Situations
782 -- 784Makoto Imase, Masaki Itoh. A Design for Directed Graphs with Minimum Diameter

Volume 32, Issue 7

603 -- 614José C. Barros, Brian W. Johnson. Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay
615 -- 621Chin-Long Chen. Error-Correcting Codes with Byte Error-Detection Capability
621 -- 637Michael C. McFarland, Alice C. Parker. An Abstract Model of Behavior for Hardware Descriptions
637 -- 648Dharma P. Agrawal. Graph Theoretical Analysis and Design of Multistage Interconnection Networks
649 -- 657Gerald M. Masson, S. Brent Morris. Expected Capacity of (m over 2)-Networks
657 -- 666Christoph von Conta. Torus and Other Networks as Communication Networks With Up to Some Hundred Points
667 -- 677Jean-Loup Baer, Hung-Chang Du, Richard E. Ladner. Binary Search in a Multiprocessing Environment
677 -- 683Leon E. Winslow, Yuan-Chieh Chow. The Analysis and Design of Some New Sorting Machines
684 -- 688Gérard M. Baudet, Franco P. Preparata, Jean Vuillemin. Area-Time Optimal VLSI Circuits for Convolution
689 -- 695K. O. Siomalas, B. A. Bowen. Performance of Cross-Bar Multiprocessor Systems
695 -- 696Alexander Miczo. A Self-Test Hardwired Control Section

Volume 32, Issue 6

521 -- 526Louis B. Bushard. A Minimum Table Size Result for Higher Radix Nonrestoring Division
526 -- 534Earl E. Swartzlander Jr., D. V. Satish Chandra, H. Troy Nagle Jr., Scott A. Starks. Sign/Logarithm Arithmetic for FFT Implementation
535 -- 542Larry A. Dunning, Murali R. Varanasi. Code Constructions for Error Control in Byte Organized Memory Systems
543 -- 550Kostas N. Oikonomou, Richard Y. Kain. Abstractions for Node Level Passive Fault Detection in Distributed Systems
551 -- 557K. S. Ramanatha, Nripendra N. Biswas. A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays
557 -- 569Robert J. Sheraga, John L. Gieser. Experiments in Automatic Microcode Generation
569 -- 581Dhruva Nath, S. N. Maheshwari, P. C. P. Bhatt. Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees
582 -- 585Ellis Horowitz, Alessandro Zorat. Divide-and-Conquer for Parallel Processing
585 -- 589David A. Carlson. Time-Space Tradeoffs on Back-to-Back FFT Algorithms
590 -- 594Zenon D. Ulman. Sign Detection and Implicit-Explicit Conversion of Numbers in Residue Arithmetic
597 -- 598Robert G. Cantarella. The Reliability of Periodically Repaired ::::n - l/n:::: Parallel Redundant Systems

Volume 32, Issue 5

425 -- 438Joseph E. Requa, James R. McGraw. The Piecewise Data Flow Architecture: Architectural Concepts
438 -- 444K. S. Ramanatha, Nripendra N. Biswas. An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays
444 -- 450David Steinberg. Invariant Properties of the Shuffle-Exchange and a Simplified Cost-Effective Version of the Omega Network
451 -- 463Alexandre Brandwajn. Models of DASD Subsystems with Multiple Access Paths: A Throughput-Driven Approach
464 -- 475K. V. S. S. Prasad Rao, Dhruba Basu. Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains
476 -- 478James Leslie Keedy. An Instruction Set for Evaluating Expressions
478 -- 487Marco Mezzalama, Paolo Prinetto. A Hierarchical Description Model for Microcode
487 -- 494Philipp W. Besslich. A Method for the Generation and Processing of Dyadic Indexed Data
494 -- 497Nikolaos Gaitanis, Constantin Halatsis. Near-Perfect Codes for Binary-Coded Radix-::::r:::: Arithmetic Units
497 -- 500G. R. Blakley. A Computer Algorithm for Calculating the Product A::::B:::: Modulo ::::M::::
501 -- 504Fred J. Taylor. An Overflow-Free Residue Multiplier
504 -- 507Vijaya Ramachandran. Single Residue Error Correction in Residue Number Systems
507 -- 511Constantine Halatsis, Nikolaos Gaitanis, Maria Sigala. Fast and Efficient Totally Self-Checking Checkers for ::::m::::-out-of-(2::::m:::: ±1) Codes
511 -- 512Teruhiko Yamada, Takashi Nanya. Comments on Detection Location of Input and Feedback Bridging Faults Among Input Output Lines
512 -- 519Denise Amar. On the Connectivity of Some Telecommunications Networks

Volume 32, Issue 4

331 -- 337E. V. Krishnamurthy. On the Conversion of Hensel Codes to Farey Rationals
337 -- 343Antoine Froment. Error Free Computation: A Direct Method to Convert Finite-Segment ::::p::::-Adic Numbers into Rational Numbers
343 -- 351Nai-Kuan Tsao. A Simple Approach to the Error Analysis of Division-Free Numerical Algorithms
352 -- 358Osaaki Watanuki, Milos D. Ercegovac. Error Analysis of Certain Floating-Point On-Line Algorithms
359 -- 369Shauchi Ong, Daniel E. Atkins. A Basis for the Quantitative Comparison of Computer Number Systems
370 -- 377Marty S. Cohen, T. E. Hull, V. Carl Hamacher. CADAC: A Controlled-Precision Decimal Arithmetic Unit
378 -- 388Peter Kornerup, David W. Matula. Finite Precision Rational Arithmetic: An Arithmetic Unit
388 -- 396W. Kenneth Jenkins. The Design of Error Checkers for Self-Checking Residue Number Arithmetic
396 -- 398E. V. Krishnamurthy, Venu K. Murthy. Fast Iterative Division of ::::p::::-adic Numbers
398 -- 402C. H. Huang. A Fully Parallel Mixed-Radix Conversion Algorithm for Resedue Number Applications
402 -- 406Mary Jane Irwin, Robert Michael Owens. Fully Digit On-Line Networks
406 -- 411Robert Michael Owens. Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic
411 -- 417Daniel W. Lozier. The Use of Floating-Point and Interval Arithmetic in the Computation of Error Bounds
417 -- 422Janak H. Patel, Leona Y. Fung. Concurrent Error Detection in Multiply and Divide Arrays

Volume 32, Issue 3

209 -- 220Raghunath Raghavan, Sartaj Sahni. Single Row Routing
221 -- 232C. V. Ramamoorthy, Benjamin W. Wah. The Isomorphism of Simple File Allocation
232 -- 244Laurence J. Laning, Michael S. Leonard. File Allocation in a Distributed Computer Communication Network
245 -- 253Carol A. Niznik. A Quantization Approximation for Modeling Computer Network Nodal Queueing Delay
254 -- 264Manoj Kumar, Daniel S. Hirschberg. An Efficient Implementation of Batcher s Odd-Even Merge Algorithm and Its Application in Parallel Sorting Schemes
265 -- 273Christopher P. Arnold, Michael I. Parr, Michael B. Dewe. An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations
273 -- 283Nikolaos Gaitanis, Constantine Halatsis. A New Design Method for ::::m::::-Out-of-::::n:::: TSC Checkers
284 -- 293Donald F. Wann, Mark A. Franklin. Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks
294 -- 300Jean Vuillemin. A Combinatorial Limit to the Computing Power of VLSI Circuits
301 -- 306Trieu-Kien Truong, K. Y. Liu, Irving S. Reed. A Parallel-Pipeline Architecutre of the Fast Polynomial Transform for Computing a Two-Dimensional Cyclic Convolution
307 -- 315Eliezer Dekel, Sartaj Sahni. Binary Trees and Parallel Scheduling Algorithms
315 -- 319Kuang-Wei Chiang, Zvonko G. Vranesic. A Tree Representation of Combinational Networks
319 -- 323Dhiraj K. Pradhan. Sequential Network Design Using Extra Inputs for Fault Detection
323 -- 325Asok Bhattacharyya. On a Novel Approach of Fault Detection in an Easily Testable Sequential Machine with Extra Inputs and Extra Outputs
326 -- 328Constantine Halatsis, Nikolaos Gaitanis, Maria Sigala. Error-Correcting Codes in Binary-Coded Radix-::::r:::: Arithmetik

Volume 32, Issue 2

101 -- 108Gordon K. Lin, Premachandran R. Menon. Totally Preset Checking Experiments for Sequential Machines
108 -- 120Tomás Lozano-Pérez. Spatial Planning: A Configuration Space Approach
120 -- 133Gregor von Bochmann, Michel Raynal. Structured Specification of Communicating Systems
133 -- 147Yaron I. Gold, William R. Franta, Shlomo Moran. A Distributed Channel-Access Protocol for Fully-Connected Networks with Mobile Nodes
147 -- 156Gilles H. Garcia, William J. Kubitz. Minimum Mean Running Time Function Generation Using Read-Only Memory
156 -- 175Michael J. Flynn, Lee W. Hoevel. Execution Architecture: The DELtran Experiment
175 -- 189Allan Gottlieb, Ralph Grishman, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, Marc Snir. The NYU Ultracomputer - Designing an MIMD Shared Memory Parallel Computer
190 -- 194Zeev Barzilai, Don Coppersmith, Arnold L. Rosenberg. Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
194 -- 198Franco P. Preparata. A Mesh-Connected Area-Time Optimal VLSI Multiplier of Large Integers
198 -- 201Alfred K. Susskind. Testing by Verifying Walsh Coefficients
201 -- 0John P. Robinson. Addendum to Optimum Golomb Rulers
201 -- 204D. J. Evans, R. C. Dunbar. The Parallel Solution of Triangular Systems of Equations
204 -- 207Alexander R. Bazelow, Jaan Raamot. On the Microprocessor Solution of Ordinary Differential Equations Using Integer Arithmetic

Volume 32, Issue 12

1073 -- 1080Vijay Pitchumani, Edward P. Stabler. An Inductive Assertion Method for Register Transfer Level Design Verification
1081 -- 1090Laxmi N. Bhuyan, Dharma P. Agrawal. Design and Performance of Generalized Interconnection Networks
1091 -- 1098Clyde P. Kruskal, Marc Snir. The Performance of Multistage Interconnection Networks for Multiprocessors
1099 -- 1108Krishnan Padmanabhan, Duncan H. Lawrie. A Class of Redundant Path Multistage Interconnection Networks
1109 -- 1117Mandayam A. Srinivas. Optimal Parallel Scheduling of Gaussian Elimination DAG s
1118 -- 1127Robert Geist, Kishor S. Trivedi. Ultrahigh Reliability Prediction for Fault-Tolerant Computer Systems
1128 -- 1136Paul Chow, Zvonko G. Vranesic, Jui Lin Yen. A Pipelined Distributed Arithmetic PFFT Processor
1137 -- 1144Hideo Fujiwara, Takeshi Shimono. On the Acceleration of Test Generation Algorithms
1145 -- 1150Donald T. Tang, Lin S. Woo. Exhaustive Test Pattern Generation with Constant Weight Vectors
1151 -- 1159Özalp Babaoglu, Domenico Ferrari. Two-Level Replacement Decisions in Paging Stores
1160 -- 1170Philip S. Liu, Tzay Y. Young. VLSI Array Design Under Constraint of Limited I/O Bandwidth
1171 -- 1184Clark D. Thompson. The VLSI Complexity of Sorting
1185 -- 1188David W. Twigg. Transposition of Matrix Stored on Sequential File
1188 -- 1191Steven M. Kramer, Deepinder P. Sidhu. Security Information Flow in Multidimensional Arrays
1191 -- 1194Ralph Grishman, Bogong Su. A Preliminary Evaluatin of Trace Scheduling for Global Microcode Compaction
1194 -- 1198Mark G. Karpovsky. Universal Tests for Detection of Input/Output Stuck-At and Bridging Faults
1198 -- 1200Jacob Savir. Good Controllability and Observability Do Not Guarantee Good Testability
1200 -- 1201C. E. Veni Madhavan, S. Krishna. Comments on Optimal Design of Distributed Information Systems
1201 -- 1203Kevin W. Bowyer, C. Frank Starmer. Optimizing Contiguous-Element Region Selection for Virtual Memory Systems
1203 -- 1207Francis Y. L. Chin, Cao An Wang. Optimal Algorithms for the Intersection and the Minimum Distance Problems Between Planar Polygons
1207 -- 1209Thomas J. Chaney. Measured Flip-Flop Responses to Marginal Triggering
1209 -- 1211Ralph Kallman. A Faster 8-Bit Carry Circuit
1211 -- 1212Bernard M. E. Moret, Michael G. Thomason, Rafael C. Gonzalez. Symmetric and Threshold Boolean Functions Are Exhaustive

Volume 32, Issue 11

977 -- 989Yuval Tamir, Carlo H. Séquin. Strategies for Managing the Register File in RISC
989 -- 1001Hari K. Nagpal, Graham A. Jullien, William C. Miller. Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field Arithmetic
1002 -- 1012Werner E. Kluge. Cooperating Reduction Machines
1013 -- 1028Dale D. Miller, John N. Polky. A Residue Number System Implementation of the LMS Algorithm Using Optical Waveguide Circuits
1029 -- 1037Gabriel M. Silberman. Delayed-Staging Hierarchy Optimization
1038 -- 1046Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara. An Easily Testable Design of Programmable Logic Arrays for Multiple Faults
1047 -- 1057Clark D. Thompson. Fourier Transforms in VLSI
1058 -- 1062D. Michael Miller, Jon C. Muzio. Spectral Fault Signatures for Internally Unate Combinational Networks
1062 -- 1064Simon S. Lam. A Simple Derivation of the MVA and LBANC Algorithms from the Convolution Algorithm
1064 -- 1067Wm. Randolph Franklin. Efficient Iterated Rotation of an Object
1067 -- 1069Per-Erik Danielsson. A Variable-Lengt Shift-Register
1069 -- 1071Subhash C. Kak. A Structural Redundancy in ::::d::::-Sequences

Volume 32, Issue 10

881 -- 902Eric M. Aupperle. Merit s Evolution - Statistically Speaking
902 -- 910Arnold L. Rosenberg. The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
911 -- 922A. Pedar, V. V. S. Sarma. Architecture Optimization of Aerospace Computing Systems
922 -- 933Sadahiro Isoda, Yoshizumi Kobayashi, Toru Ishida. Global Compaction of Horizontal Microprogams Based on the Generalized Data Dependency Graph
933 -- 941Roger W. Hockney. Characterizing Computers and Optimizing the FACR(::::l::::) Poisson-Solver on Parallel Unicomputers
942 -- 946Clyde P. Kruskal. Searching, Merging, and Sorting in Parallel Computation
947 -- 952Daniel Brand. Redundancy and Don t Cares in Logic Synthesis
953 -- 957Anton T. Dahbura, Gerald M. Masson. Greedy Diagnosis as the Basis of an Intermittent-Fault/Transient-Upset Tolerant System Design
957 -- 959El Mostapha Aboulhamid, Eduard Cerny. A Class of Test Generators for Built-In Testing
960 -- 961Jacob Savir. A New Empirical Test for the Quality of Random Integer Generators
961 -- 968Christos A. Papachristou. Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach
969 -- 976Akito Sakurai, Saburo Muroga. Parallel Binary Adders with a Minimum Number of Connections

Volume 32, Issue 1

4 -- 14Zary Segall, Ajay Singh, Richard T. Snodgrass, Anita K. Jones, Daniel P. Siewiorek. An Integrated Instrumentation Environment for Multiprocessors
15 -- 31Hansjörg Fromm, Uwe Hercksen, Ulrich Herzog, Karl-Heinz John, Rainer Klar, Wolfgang Kleinöder. Experiences with Performance Measurement and Modeling of a Processor Array
32 -- 37Dennis Parkinson, Heather M. Liddell. The Measurement of Performance on a Highly Parallel System
38 -- 47Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson. Shared Cache for Multiple-Stream Computer Systems
48 -- 59Faye A. Briggs, Michel Dubois. Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
60 -- 72Marco Ajmone Marsan, Gianfranco Balbo, Gianni Conte, Francesco Gregoretti. Modeling Bus Contention and Memory Interference in a Multiprocessor System
73 -- 82Philip Heidelberger, Kishor S. Trivedi. Analytic Queueing Models for Programs with Internal Concurrency
83 -- 95Daniel A. Reed, Herbert D. Schwetman. Cost-Performance Bounds for Multimicrocomputer Networks
96 -- 98Isi Mitrani, Peter J. B. King. Multiserver-Systems Subject to Breakdowns: An Empirical Study