Robert Harper - researchr profile publications

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Publications tagged layout

An Intelligent Clustering Algorithm for 3D Objects Layouts in Storage SystemsShao-Shin Hung, Hui-Ling Lin. mue 2008: 294-297 [doi]

Document layout and color driven image retrievalPere Obrador. sigir 2007: 889-890 [doi]

Towards Generic Layouts for Multi-Channel Publishing: XF-Extensible Formatting Heli Tervo, Anne Honkaranta, Paula Leinonen. ista 2006: 165-176

Information extraction from calls for papers with conditional random fields and layout featuresKarl-Michael Schneider. air, 25(1-2):67-77, 2006. [doi]

Layout of an Arbitrary Permutation in a Minimal Right Triangle AreaMaria Artishchev-Zapolotsky, Shimon Even, Vladimir Yanovski. pdpta 2005: 124-130

SAN Virtualization Layout and PerformanceBruce McNutt. cmg 2004: 933-940

Supporting Collaborative Layouting in Word ProcessingThomas B. Hodel, Dominik Businger, Klaus R. Dittrich. coopis 2004: 355-372 [doi]

Layout Volumes of the HypercubeLubomir Torok, Imrich Vrto. gd 2004: 414-424 [doi]

Complex products and systems: Potential from using layout platformsAdrian P. Hofer, Johannes I. M. Halman. aiedam, 18(1):55-69, 2004. [doi]

A type theory for memory allocation and data layoutLeaf Petersen, Robert Harper, Karl Crary, Frank Pfenning. POPL 2003: 172-184 [doi]

Layout impact of resolution enhancement techniques: impediment or opportunity?Lars Liebmann. ispd 2003: 110-117 [doi]

Layout Area of the HypercubeShimon Even, Roni Kupershtok. join, 4(4):395-417, 2003. [doi]

Web User s Interfaces LayoutMarconi Luiz França, Bernardo Lula Jr.. iadis 2002: 491-494

Layout area of the hypercube (extended abstract)Shimon Even, Roni Kupershtok. soda 2002: 366-371 [doi]

On three-dimensional layout of pyramid networksT. Yamada, N. Fujii, S. Ueno. apccas 2002: 159-164 [doi]

Turbo recognition: decoding page layoutTaku A. Tokuyasu. JCDL 2001: 475 [doi]

Area efficient layouts of the Batcher sorting networksShimon Even. networks, 38(4):199-208, 2001. [doi]

Layout of Two Dimensional Irregular Shapes Using Genetic AlgorithmsRym M Hallah, Ahlem Bouziri, Walid Jilani. ieaaie 2001: 403-411 [doi]

Automated Layout of Concept Lattices Using Layered Diagrams and Additive DiagramsRichard Cole. acsc 2001: 47-53 [doi]

Automated Layout of Concept Lattices Using Force Directed Placement and Genetic AlgorithmsRichard Cole. acsc 2000: 31-42 [doi]

Dynamic spatial layout in graphical user interfacesMaximilian Stempfhuber. hci 1999: 137-141

A timing-driven floorplanning algorithm with the Elmore delay model for building block layoutTetsushi Koide, Shin ichi Wakabayashi. integration, 27(1):57-76, 1999. [doi]

Space and Time-Efficient Memory Layout for Multiple InheritancePeter F. Sweeney, Joseph Gil. OOPSLA 1999: 256-275 [doi]

System Support for Dynamic Layout of Distributed ApplicationsOphir Holder, Israel Ben-Shaul, Hovav Gazit. icdcs 1999: 403-411 [doi]

Dynamic Layout of Distributed Applications in FarGoOphir Holder, Israel Ben-Shaul, Hovav Gazit. ICSE 1999: 163-173 [doi]

Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout DataKatsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka. ats 1997: 162-167 [doi]

Layout and Language: Preliminary Investigations in Recognizing the Structure of TablesMatthew Hurst, Shona Douglas. icdar 1997: 1043-1047 [doi]

Layout Algorithms for VLSI deisgnAndrea S. LaPaugh. ACM Comput. Surv., 28(1):59-61, 1996.

A Linear Iteration Time Layout Algorithm for Visualising High-Dimensional DataMatthew Chalmers. visualization 1996: 127-132

Strategic Layout Planning and Simulation for Lean Manufacturing: A LayOPT TutorialEric S. Grajo. wsc 1996: 564-568 [doi]

Document Type Independent Tools: Common Services for Manipulation, Layout, and User SupportBernhard Westfechtel. ipsen 1996: 208-221

Strategic Layout Planning and Simulation for Lean Manufacturing a LayOPT TutorialEric S. Grajo. wsc 1995: 510-514 [doi]

KLaGen - A Generator of Static CMOS-cell Layout from Circuit SchematicsKarol Doerffer, Attila T. Téby, Oskar Anton, Dieter A. Mlynski. iscas 1993: 1845-1848

ABLE: AMD Backplane for Layout EnginesKenneth W. Wan, Roshan A. Gidwani. dac 1993: 556-560 [doi]

Corner-stitched tiles with curved boundaries [circuit layout]Carlo H. Séquin, Heloisa da Silva Facanha. tcad, 12(1):47-58, 1993. [doi]

Automatic extraction of circuit models from layout artwork for a BiCMOS technologyTerence B. Hook. tcad, 11(6):732-738, 1992. [doi]

Distributed Layout Verification Using Sequential Software and Standard HardwareYehuda Shiran. itc 1991: 1009-1015

A framework for industrial layout generatorsWayne Bower, Carl Seaquist, Wayne Wolf. tcad, 10(5):596-603, 1991. [doi]

Layout of Flexible Manufacturing Systems - Selected ProblemsHartmut Noltemeier. cga 1991: 217-225

Hierarchical layout verification for submicron designsW. Meier. eurodac 1990: 382-386 [doi]

Einsatzmöglichkeiten algorithmischer Layout-BeschreibungenWolfgang Rülling. ife, 5(1):20-34, 1990.

SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layoutsJoel W. Gannett. tcad, 9(6):669-674, 1990. [doi]

Template Style Considerations for Sea-of-Gates Layout GenerationG. D. Adams, Carlo H. Séquin. dac 1989: 31-36 [doi]

Simulation and layout of a laser radar production facilityS. J. Lehman, W. R. Davison. wsc 1989: 892-895 [doi]

Parallel Processing and Document LayoutHeather Brown. epodd, 1(2):97-104, 1988.

A Dynamic and Efficient Representation of Building-Block LayoutWayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh. dac 1987: 376-384 [doi]

Optimal Layouts of the Tree of Meshes with Vertices on the Perimeter of the Bounding Convex RegionOndrej Sýkora, Imrich Vrto. STACS 1984: 209-217

PSI: A Symbolic Layout SystemRolf-Dieter Fiebrich, Yuh-Zen Liao, George M. Koppelman, Edward N. Adams. ibmrd, 28(5):572-580, 1984.

A VLSI Layout for a Pipelined Dadda MultiplierPeter R. Cappello, Kenneth Steiglitz. tocs, 1(2):157-174, 1983. [doi]

The Complexity of Compacting Hierarchically Specified Layouts of Integrated Circuits (Preliminary Version)Thomas Lengauer. focs 1982: 358-368

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