The following publications are possibly variants of this publication:
- Efficient Modular Testing of SOCs Using Dual-Speed TAM ArchitecturesAnuja Sehgal, Krishnendu Chakrabarty. date 2004: 422-427 [doi]
- Efficient Wrapper/TAM Co-Optimization for Large SOCsVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen. date 2002: 491-498 [doi]
- TAM Optimization for Mixed-Signal SOCs using Analog Test WrappersAnuja Sehgal, Sule Ozev, Krishnendu Chakrabarty. iccad 2003: 95-99 [doi]
- A Unified Approach for SOC Testing Using Test Data Compression and TAM OptimizationVikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty. date 2003: 11188-11190 [doi]
- Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCsSudarshan Bahukudumbi, Krishnendu Chakrabarty. tcad, 28(1):111-120, 2009. [doi]
- Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCsSudarshan Bahukudumbi, Krishnendu Chakrabarty. vlsid 2007: 459-464 [doi]
- Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCsVikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen. dac 2002: 685-690 [doi]