The following publications are possibly variants of this publication:
- An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration CircuitMinoru Watanabe, Fuminori Kobayashi. ipps 2005: [doi]
- An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSIMinoru Watanabe. socc 2007: 75-78 [doi]
- Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSIShinichi Kato, Minoru Watanabe. samos 2009: 139-148 [doi]
- A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSIMinoru Watanabe, Fuminori Kobayashi. arc 2006: 268-273 [doi]
- An optically differential reconfigurable gate array with a holographic memoryMinoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi. ipps 2006: [doi]
- A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSIM. Watanabe, F. Kobayashi. aspdac 2007: 124-125 [doi]
- A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technologyMinoru Watanabe, Fuminori Kobayashi. aspdac 2006: 108-109 [doi]
- 0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSITakahiro Watanabe, Minoru Watanabe. isvlsi 2012: 308-313 [doi]
- An 11, 424-gate dynamic optically reconfigurable gate array VLSIMao Nakajima, Minoru Watanabe. fpt 2008: 293-296 [doi]
- Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel ConfigurationSae Goto, Minoru Watanabe, Nobuya Watanabe. apccas 2021: 241-245 [doi]
- An optically reconfigurable gate array VLSI driven by an unstabilized power supply unitMasashi Tsujino, Minoru Watanabe, Nobuya Watanabe. socc 2023: 1-5 [doi]
- Total Dose Tolerance Analysis of an Optically Reconfigurable Gate Array VLSIKaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe. icecsys 2022: 1-4 [doi]