Abstract is missing.
- TPI for improving PR fault coverage of Boolean and three-state circuitsM. J. Geuzebroek, Ad J. Van de Goor. 3-8 [doi]
- On the selection of efficient arithmetic additive test pattern generators [logic test]Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, R. Rodriguez, Joan Figueras. 9-14 [doi]
- Parity-based output compaction for core-based SOCs [logic testing]Ozgur Sinanoglu, Alex Orailoglu. 15-20 [doi]
- Defect-oriented dynamic fault models for embedded-SRAMsSimone Borri, Magali Hage-Hassan, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel. 23-28 [doi]
- Importance of dynamic faults for new SRAM technologiesSaid Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. Van de Goor. 29-34 [doi]
- Yield analysis for repairable embedded memoriesAnuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty. 35-40 [doi]
- Scan test strategy for asynchronous-synchronous interfaces [SoC testing]Octavian Petre, Hans G. Kerkhoff. 43-48 [doi]
- An efficient approach to SoC wrapper design, TAM configuration and test schedulingJulien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre. 51-56 [doi]
- Control-aware test architecture design for modular SOC testingSandeep Kumar Goel, Erik Jan Marinissen. 57-62 [doi]
- A practical evaluation of I/sub DDQ/ test strategies for deep submicron production test application. Experiences and targets from the fieldAlessandra Fudoli, Alberto Ascagni, Davide Appello, Hans A. R. Manhaeve. 65-70 [doi]
- Automating the device interface board modeling for virtual testMarco Rona, Gunter Krampl, Fritz Raczkowski. 71-76 [doi]
- Signal integrity loss in bus lines due to open shielding defectsVictor Avendaño, Víctor H. Champac, Joan Figueras. 79-84 [doi]
- Process-variability aware delay fault testing of /spl Delta/V/sub T/ and weak-open defectsDaniel Arumí-Delgado, Rosa Rodríguez-Montañés, José Pineda de Gyvez, Guido Gronthoud. 85-90 [doi]
- Modeling feedback bridging faults with non-zero resistanceIlia Polian, Piet Engelke, Michel Renovell, Bernd Becker 0001. 91-96 [doi]
- Automating test program generation in STIL - expectations and experiences using IEEE 1450 [standard test interface language]Helmut Lang, Bhuwnesh Pande, Heiko Ahrens. 99-104 [doi]
- Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuitsEric Liau, Doris Schmitt-Landsiedel. 105-110 [doi]
- Code generation for functional validation of pipelined microprocessorsFulvio Corno, Giovanni Squillero, Matteo Sonza Reorda. 113-118 [doi]
- Enhanced P1500 compliant wrapper suitable for delay fault testing of embedded coresH. J. Vermaak, H. G. Kerkhoff. 121-126 [doi]
- RF ATE equipment benefit from advanced network analyzer technologyMarten Seth. 129-131 [doi]
- Characterization of the EME of integrated circuits with the help of the IEC standard 61967 [electromagnetic emission]Timm Ostermann, Bernd Deutschmann. 132-137 [doi]
- On path selection for delay fault testing considering operating conditions [logic IC testing]Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu. 141-146 [doi]
- Requirements for delay testing of look-up tables in SRAM-based FPGAsP. Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. 147-152 [doi]
- Debug architecture for system on chip taking full advantage of the test access portErik Moerman, Sébastien Bocq, Johan Verfaillie. 155-159 [doi]