Tsutomu Yoshimura - researchr alias

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Viewing Publication 1 - 26 from 26

2023

Analysis of the Electromagnetic Coupling of Two Phase-Locked LoopsRyuji Komabayashi, Tsutomu Yoshimura. iscas 2023: 1-4 [doi]

2022

Self-Coupling and Mutual Pulling in Phase-Locked LoopsTsutomu Yoshimura. tcasI, 69(8):3260-3271, 2022. [doi]

2021

Study of Injection Pulling of Oscillators in Phase-Locked LoopsTsutomu Yoshimura. tvlsi, 29(2):321-332, 2021. [doi]

Mitigation of Mutual Pulling in Two Phase-locked LoopsTsutomu Yoshimura. newcas 2021: 1-4 [doi]

2019

Digital Third-Order Nonlinearity Correction for Time-Interleaved A/D Converters with VCOsTakao Kihara, Keisuke Miyakoshi, Tsutomu Yoshimura. iscas 2019: 1-4 [doi]

Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling ReceiversTakao Kihara, Tomoya Takahashi, Tsutomu Yoshimura. tcas, 66(6):2007-2016, 2019. [doi]

2018

2017

Design of cascaded integrator-comb decimation filters for direct-RF sampling receiversTakao Kihara, Hiroyuki Yano, Tsutomu Yoshimura. iscas 2017: 1-4 [doi]

Spur reduction by self-injection loop in a fractional-N PLLMayu Kobayashi, Yuya Masui, Takao Kihara, Tsutomu Yoshimura. icecsys 2017: 260-263 [doi]

Digital correction of mismatches in time-interleaved ADCs for digital-RF receiversTomoya Takahashi, Takao Kihara, Tsutomu Yoshimura. icecsys 2017: 9-12 [doi]

2016

2015

Subharmonically injection-locked PLL with variable pulse-width injectionsShuei Morishita, Shinji Shimizu, Takao Kihara, Tsutomu Yoshimura. iscas 2015: 557-560 [doi]

2014

Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty RatioShunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda. tcas, 61-I(7):2194-2203, 2014. [doi]

Analysis and modeling of oscillators with interference noiseShinji Shimizu, Junki Mizuno, Shuei Morishita, Koichiro Hida, Tsutomu Yoshimura. icecsys 2014: 128-131 [doi]

2013

Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked LoopTsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda. tcas, 60-I(4):896-907, 2013. [doi]

2012

Utilising the normal distribution of the write noise margin to easily predict the SRAM write yieldHiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda. iet-cds, 6(4):260-270, 2012. [doi]

2011

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the DistributionHiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda. tcas, 58-II(4):230-234, 2011. [doi]

2006

A study of interference in synchronous systemsTsutomu Yoshimura, Atsushi Iwata. tcas, 53(8):1726-1740, 2006. [doi]

2004

An analysis of interference in synchronous systemsTsutomu Yoshimura, Atsushi Iwata. ieiceee, 1(15):465-471, 2004. [doi]

2002

A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technologyTsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki. cicc 2002: 355-358 [doi]

1999

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interfaceYasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada. jssc, 34(4):494-501, 1999. [doi]

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