Abstract is missing.
- Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care (Abstract)Harmke de Groot. 3 [doi]
- Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health CareHarmke de Groot, Maryam Ashouei, Julien Penders, Valer Pop, Maja Vidojkovic, Bert Gyselinckx, Refet Firat Yazicioglu. 4-10 [doi]
- Cryptographic Contests: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms in Hardware (Abstract)Kris Gaj. 11 [doi]
- The Future of Data-Parallel Embedded Systems (Abstract)Menno Lindwer. 12 [doi]
- Generalized If-Then-Else Operator for Compact Polynomial Representation of Multi Output FunctionsIlya Levin, Osnat Keren. 15-20 [doi]
- On the Cascade Implementation of Multiple-Output Sparse Logic FunctionsVáclav Dvorák, Petr Mikusek. 21-28 [doi]
- On Failure Rate Assessment Using an Executable Model of the SystemMohammad Hossein Neishaburi, Zeljko Zilic. 29-36 [doi]
- A Cost Effective Centralized Adaptive Routing for Networks-on-ChipRan Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer. 39-46 [doi]
- Realization and Scalability of Release and Protected Release Consistency Models in NoC Based SystemsAbdul Naeem, Axel Jantsch, Xiaowen Chen, Zhonghai Lu. 47-54 [doi]
- Numeral-Based Crosstalk Avoidance Coding to Reliable NoC DesignMansour Shafaei, Ahmad Patooghy, Seyed Ghassem Miremadi. 55-62 [doi]
- A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort CommunicationHaoyuan Ying, Ashok Jaiswal, Thomas Hollstein, Klaus Hofmann. 63-70 [doi]
- Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable ArchitectureFahimeh Jafari, Shuo Li, Ahmed Hemani. 73-80 [doi]
- VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAsBehzad Salami, Morteza Saheb Zamani, Ali Jahanian. 81-87 [doi]
- PUMA: Placement Unification with Mapping and Guaranteed Throughput Allocation on an FPGA Using a Hardwired NoCMuhammad Aqeel Wahlah, Kees Goossens. 88-96 [doi]
- Improved Power Modeling of DDR SDRAMsKarthik Chandrasekar 0001, Benny Akesson, Kees Goossens. 99-108 [doi]
- Path-Based Dynamic Voltage and Frequency Scaling Algorithms for Multiprocessor Embedded Applications with Soft Delay DeadlinesAlice M. Tokarnia, Pedro C. F. Pepe, Leandro D. Pagotto. 109-116 [doi]
- Power Minimisation for Real-Time Dataflow ApplicationsAndrew Nelson, Orlando Moreira, Anca Mariana Molnos, Sander Stuijk, Ba Thang Nguyen, Kees Goossens. 117-124 [doi]
- VHDL Code Generation from Formal Event-B ModelsSergey Ostroumov, Leonidas Tsiopoulos. 127-134 [doi]
- Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply VoltageBo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez. 135-139 [doi]
- Hardware Reuse in Modern Application-Specific Processors and AcceleratorsAlexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França. 140-147 [doi]
- Quaternary High Performance Arithmetic Logic Unit DesignA. N. Nagamani, S. Nishchai. 148-153 [doi]
- Low-Latency and Low-Overhead Mesochronous and Plesiochronous SynchronizersJean-Michel Chabloz, Ahmed Hemani. 157-164 [doi]
- Towards an Efficient NoC Topology through Multiple Injection PortsJesus Camacho, José Flich, José Duato, Hans Eberle, Wladek Olesinski. 165-172 [doi]
- LastZ: An Ultra Optimized 3D Networks-on-Chip ArchitectureAmir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 173-180 [doi]
- Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded SystemsCharly Bechara, Nicolas Ventroux, Daniel Etiemble. 181-187 [doi]
- SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay FaultsRoland Dobai, Marcel Baláz. 191-196 [doi]
- Adaptive Temperature-Aware SoC Test Scheduling Considering Process VariationNima Aghaee, Zebo Peng, Petru Eles. 197-204 [doi]
- Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics PrinciplesRichard Ruzicka, Vaclav Simek. 205-212 [doi]
- A Technique for Accelerating Injection of Transient Faults in Complex SoCsAlireza Rohani, Hans G. Kerkhoff. 213-220 [doi]
- SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant SystemsMartin Straka, Jan Kastil, Zdenek Kotásek. 223-230 [doi]
- Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA SystemsFarid Lahrach, Abderrahim Doumar, Eric Châtelet. 231-238 [doi]
- Reliability-Aware Design Optimization for Multiprocessor Embedded SystemsJia Huang, Jan Olaf Blech, Andreas Raabe, Christian Buckl, Alois Knoll. 239-246 [doi]
- Design of Asynchronous Circuits on FPGAs for Soft Error ToleranceYu Bai, Weidong Kuang. 247-253 [doi]
- HMMER Performance Model for Multicore ArchitecturesSebastian Isaza, Ernst Houtgast, Georgi Gaydadjiev. 257-261 [doi]
- Kactus2: Environment for Embedded Product Development Using IP-XACT and MCAPIAntti Kamppi, Lauri Matilainen, Joni-Matti Määttä, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen. 262-265 [doi]
- 10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption StandardPaolo Maistri, Régis Leveugle. 266-269 [doi]
- Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics ProcessorsGeorgios Keramidas, Nikolaos Strikos, Stefanos Kaxiras. 270-273 [doi]
- Power Spectral Density Side Channel Attack Overlapping Window MethodPhilip Hodgers, Keanhong Boey, Máire O'Neill. 274-278 [doi]
- Dynamic Power Estimation for Motion Estimation HardwareCaglar Kalaycioglu, Ilker Hamzaoglu. 279-282 [doi]
- A Module for Packet Hijacking in NetFPGA PlatformAlfio Lombardo, Carla Panarello, Diego Reforgiato Recupero, Enrico Santagati, Giovanni Schembra. 283-286 [doi]
- Fault Models Usability Study for On-line Tested FPGAJaroslav Borecky, Martin Kohlík, Pavel Kubalík, Hana Kubatova. 287-290 [doi]
- Hardware Implementation of a Flexible Tag Platform for Passive RFID DevicesThomas Plos, Martin Feldhofer. 293-300 [doi]
- Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional AdderJiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens. 301-308 [doi]
- An Overlapped Block Motion Compensation Hardware for Frame Rate ConversionTevfik Zafer Ozcan, Cagla Cakir, Mert Cetin, Ilker Hamzaoglu. 309-315 [doi]
- Cost of Sparse Mesh Layouts Supporting Throughput ComputingMartti Forsell, Ville Leppänen, Martti Penttonen. 316-323 [doi]
- An Environment for (re)configuration and Execution Managenment of Flexible Radio PlatformsPierre-Henri Horrein, Christine Hennebert, Frédéric Pétrot. 327-334 [doi]
- FBMC and GFDM Interference Cancellation Schemes for Flexible Digital Radio PHY DesignRohit Datta, Gerhard Fettweis, Zsolt Kollar, Péter Horváth 0002. 335-339 [doi]
- A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC DecoderMuhammad Awais, Ashwani Singh, Emmanuel Boutillon, Guido Masera. 340-347 [doi]
- A Non-Intrusive Online FPGA Test Scheme Using a Hardwired Network on ChipMuhammad Aqeel Wahlah, Kees Goossens. 351-359 [doi]
- Techniques for SAT-Based Constrained Test Pattern GenerationJiri Balcarek, Petr Fiser, Jan Schmidt. 360-366 [doi]
- On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan CircuitsMichal Rumplík, Josef Strnadel. 367-374 [doi]
- An Enhanced Path Delay Fault Simulator for Combinational CircuitsPalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. 375-381 [doi]
- Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage ScalingFarshad Firouzi, Amir Yazdanbakhsh, Hamed Dorosti, Sied Mehdi Fakhraie. 385-392 [doi]
- Design of Fault Tolerant Network Interfaces for NoCsLeandro Fiorin, Laura Micconi, Mariagiovanna Sami. 393-400 [doi]
- Designing Robust Asynchronous Circuits Based on FinFET TechnologyFataneh Jafari, Mahdi Mosaffa, Siamak Mohammadi. 401-408 [doi]
- Analyzing Area Penalty of 32-Bit Fault Tolerant ALU Using BCH CodeVahid Khorasani, Bijan Vosoughi Vahdat, Mohammad Mortazavi. 409-413 [doi]
- Low Power FPGA Implementations of JH and Fugue Hash FunctionsGeorge Provelengios, Nikolaos S. Voros, Paris Kitsos. 417-421 [doi]
- Mutant Fault Injection in Functional Properties of a Model to Improve Coverage MetricsAli Abbasinasab, Mehdi Mohammadi, Siamak Mohammadi, Svetlana N. Yanushkevich, Michael Smith. 422-425 [doi]
- A Unified Architecture for BCD and Binary Adder/SubtractorChetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. 426-429 [doi]
- Synthesizing Concurrent Synchronous Computing Machines from Interrupt-Driven BinariesMichael D. Wilder, Robert Rinker. 430-433 [doi]
- Architectures for Fast Modular MultiplicationAhmet Aris, Siddika Berna Örs, Gökay Saldamli. 434-437 [doi]
- Transaction Level Modeling of a Networked Embedded System Based on a Power Line Communication ProtocolTakieddine Majdoub, Sébastien LeNours, Olivier Pasquier, Fabienne Nouvel. 438-441 [doi]
- Nexus: Hardware Support for Task-Based ProgrammingCor Meenderinck, Ben H. H. Juurlink. 442-445 [doi]
- Evaluation of Fault-Tolerant Routing Methods for NoC ArchitecturesMojtaba Valinataj. 446-449 [doi]
- On the Design of Modulo 2^n+1 MultipliersConstantinos Efstathiou, Kiamal Z. Pekmestzi, Nicholas Axelos. 453-459 [doi]
- Binary-to-RNS Conversion Units for moduli {2^n ± 3}Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa. 460-467 [doi]
- Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal ConversionEvangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos. 468-475 [doi]
- Automated Design Debugging in a Testbench-Based Verification EnvironmentMehdi Dehbashi, André Sülflow, Görschwin Fey. 479-486 [doi]
- Efficient Fault Simulation of SystemC DesignsWeiyun Lu, Martin Radetzki. 487-494 [doi]
- Higher-Order Abstraction in Hardware Descriptions with C?aSHMarco Gerards, Christiaan Baaij, Jan Kuper, Matthijs Kooijman. 495-502 [doi]
- Thermal Effect of TSVs in 3D Die-Stacked Integrated CircuitsHadrien A. Clarke, Kazuaki Murakami. 503-508 [doi]
- A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU ImplementationsAlexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak. 511-518 [doi]
- Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-SpotsRomain Prolonge, Fabien Clermidy, Leonel Tedesco, Fernando Moraes. 519-524 [doi]
- Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP ProcessorsJaroslav Sykora, Leos Kafka, Martin Danek, Lukas Kohout. 525-532 [doi]
- Pre-silicon Characterization of NIST SHA-3 Final Round CandidatesXu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont. 535-542 [doi]
- Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 AlgorithmsIgnacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval. 543-549 [doi]
- Modular Fault Injector for Multiple Fault Dependability and Security EvaluationsJohannes Grinschgl, Armin Krieg, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 550-557 [doi]
- Breaking Hitag2 with Reconfigurable HardwarePetr Stembera, Martin Novotný. 558-563 [doi]
- Iteration-Based Trade-Off Analysis of Resource-Aware SDFYang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal. 567-574 [doi]
- SoC and Board Modeling for Processor-Centric Board TestingAnton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze. 575-582 [doi]
- Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph SchedulingMorteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal. 583-590 [doi]
- Efficient CRT RSA with SCA CountermeasuresApostolos P. Fournaris, Odysseas G. Koufopavlou. 593-599 [doi]
- Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction LevelDaniel Mueller-Gritschneder, Kun Lu, Ulf Schlichtmann. 600-607 [doi]
- HDL-Mutation Based Simulation Data Generation by Propagation Guided SearchTao Xie, Wolfgang Müller 0003, Florian Letombe. 608-615 [doi]
- On-chip Monitoring: A Light-Weight Interconnection Network ApproachPablo Ituero, Marisa López-Vallejo, M. A. S. Marcos, Carlos Gómez Osuna. 619-625 [doi]
- Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based ArchitecturesKhalid Latif 0002, Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Tiberiu Seceleanu, Pasi Liljeberg, Hannu Tenhunen. 626-633 [doi]
- Formal Modeling of Multicast Communication in 3D NoCsMaryam Kamali, Luigia Petre, Kaisa Sere, Masoud Daneshtalab. 634-642 [doi]
- Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC'sKameswar Rao Vaddina, Amir-Mohammad Rahmani, Khalid Latif 0002, Pasi Liljeberg, Juha Plosila. 643-648 [doi]
- A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAsXin Xin, Jens-Peter Kaps, Kris Gaj. 651-657 [doi]
- A Unified Multiply/Accumulate Unit for Pairing-Based Cryptography over Prime, Binary and Ternary FieldsTobias Vejda, Johann Großschädl, Dan Page. 658-666 [doi]
- A Novel Architecture of Implementing Error Detecting AES Using PRNSJunfeng Chu, Mohammed Benaissa. 667-673 [doi]
- How a Symmetry Metric Assists Side-Channel Evaluation - A Novel Model Verification Method for Power AnalysisAnnelie Heuser, Michael Kasper, Werner Schindler, Marc Stöttinger. 674-681 [doi]
- Rapid and Accurate Leakage Power Estimation for Nano-CMOS CircuitsMichal Bryk, Lech Józwiak, Wieslaw Kuzmicz. 685-692 [doi]
- An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power GatingIttetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor. 693-700 [doi]
- A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear InterpolationsSatoru Nakano, Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi. 701-707 [doi]
- Exploiting Inter and Intra Application Dynamism to Save EnergyMartijn Koedam, Sander Stuijk, Henk Corporaal. 708-715 [doi]
- Model Driven Cache-Aware Scheduling of Object Oriented Software for Chip MultiprocessorsTolga Ovatman, Feza Buzluca. 719-726 [doi]
- Compiling Esterel for Multi-core ExecutionSimon Yuan, Li Hsien Yoong, Partha S. Roop. 727-735 [doi]
- Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore ProcessorsLina Sawalha, Sonya Wolff, Monte P. Tull, Ronald D. Barnes. 736-745 [doi]
- Energy Behaviour of NUCA Caches in CMPsAlessandro Bardine, Pierfrancesco Foglia, Francesco Panicucci, Marco Solinas, Julio Sahuquillo. 746-753 [doi]
- A Wearable Intelligent System for the Health of Expectant Mom's and of Their ChildrenGiovanni Danese, Francesco Leporati, Alessandra Majani, Giulia Matrone, Enrico Merlino. 757-763 [doi]
- Embedded System for Camera-Based TV Power ReductionChoong Geun Lee, Vasily G. Moshnyaga, Koji Hashimoto. 764-768 [doi]
- An Embedded Video Sensor for a Smart Traffic LightGuido Matrella, Davide Marani. 769-776 [doi]
- On the Efficiency of Design Time Evaluation of the Resistance to Power AttacksAlessandro Barenghi, Guido Bertoni, Fabrizio De Santis, Filippo Melzani. 777-785 [doi]
- Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow MonitoringMohammad Maghsoudloo, Hamid R. Zarandi, Saadat Pour-Mozafari, Navid Khoshavi. 789-792 [doi]
- Automatic Interface Generation for Component Reuse in HW-SW PartitioningNicola Bombieri, Franco Fummi, Sara Vinco, Davide Quaglia. 793-796 [doi]
- A Scalable Distributed Asynchronous Control Network for High Level Synthesis of Digital CircuitsTom Van Leeuwen 0002, Rene van Leuken. 797-800 [doi]
- A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle RoutersYohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 801-804 [doi]
- Faster Processor Allocation Algorithms for Mesh-Connected CMPsLuka B. Daoud, M. El-Sayed Ragab, Victor Goulart. 805-808 [doi]
- Compatibility Study of Compile-Time Optimizations for Power and ReliabilityGhazaleh Nazarian, Christos Strydis, Georgi Gaydadjiev. 809-813 [doi]
- An FPGA Implementation of the ZUC Stream CipherParis Kitsos, Nicolas Sklavos, Athanassios N. Skodras. 814-817 [doi]
- A Unified Execution Model for Data-Driven Applications on a Composable MPSoCAshkan Beyranvand Nejad, Anca Mariana Molnos, Kees G. W. Goossens. 818-822 [doi]