Abstract is missing.
- CUSTARD - A Customisable Threaded FPGA Soft Processor and ToolsRobert G. Dimond, Oskar Mencer, Wayne Luk. 1-6
- A Reconfigurable Instruction Memory Hierarchy for Embedded SystemsZhiguo Ge, Hock-Beng Lim, Weng-Fai Wong. 7-12
- Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia ProcessorMarco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello. 13-18
- FPGA PLB Evaluation using Quantified Boolean SatisfiabilityAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown. 19-24
- FELIX: Using Rewriting-Logic for Generating Functionally Equivalent ImplementationsCarlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein. 25-30
- Post-Placement BDD-Based Decomposition for FPGAsValavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown. 31-38
- Hashing + Memory = Low Cost, Exact Pattern MatchingGiorgos Papadopoulos, Dionisios N. Pnevmatikatos. 39-44
- High-speed and Memory Efficient TCP Stream Scanning using FPGAYutaka Sugawara, Mary Inaba, Kei Hiraki. 45-50
- Mutable Codesign for Embedded Protocol ProcessingTodd S. Sproull, Gordon J. Brebner, Christopher E. Neely. 51-56
- Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable ProcessorChi-Wei Wang, Nicholas P. Carter, Richard B. Kujoth, Jeffrey J. Cook, Derek B. Gottlieb. 57-64
- Applying the Small-World Network to Routing Structure of FPGAsHisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi. 65-70
- MILP-based Placement and Routing for Dataflow ArchitectureMichael B. Healy, Mongkol Ekpanyapong, Sung Kyu Lim. 71-76
- Using DSP Blocks For ROM Replacement: A Novel Synthesis FlowGareth W. Morris, George A. Constantinides, Peter Y. K. Cheung. 77-82
- An FPGA Solver for WSAT AlgorithmsKenji Kanazawa, Tsutomu Maruyama. 83-88
- An Efficient and Scalable Architecture for Neural Networks with Backpropagation LearningPedro Domingos, Fernando M. Silva, Horácio C. Neto. 89-94
- Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoCMark Holland, Scott Hauck. 95-100
- A 11 GHz FPGA with Test ApplicationsChao You, Jong-Ru Guo, Michael Chu, Russell P. Kraft, Bryan S. Goda, John F. McDonald. 101-105
- Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia PurposesFrancisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei. 106-111
- Power and Area Optimization for Multiple Restricted MultiplicationNalin Sidahao, George A. Constantinides, Peter Y. K. Cheung. 112-117
- Programmable Numerical Function Generators: Architectures and Synthesis MethodTsutomu Sasao, Shinobu Nagayama, Jon T. Butler. 118-123
- Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable LogicChun Te Ewe, Peter Y. K. Cheung, George A. Constantinides. 124-129
- Real-time Handel-C Based Implementation of DV DecoderMarek Gorgon, Slawomir Cichon, Miroslaw Pac. 130-135
- Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing SystemsNajeem Lawal, Benny Thörnberg, Mattias O Nils. 136-141
- Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image ProcessingSuhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk. 142-147
- A Dynamically Reconfigurable Bluetooth Base Band UnitJohn Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Wang Jiang Chau. 148-152
- DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable DevicesChristophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen. 153-158
- Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building BlocksAndy Gean Ye, Jonathan Rose. 159-166
- Timing Aware Interconnect Prediction Models for FPGAsShankar Balachandran, Dinesh Bhatia. 167-172
- Multidimensional Dynamic Programming for Homology SearchShingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya. 173-178
- Real-time Generation of Three-Dimensional Motion FieldsHiroaki Niitsuma, Tsutomu Maruyama. 179-184
- Evaluation of Ray Casting on Processor-Like Reconfigurable ArchitecturesTobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel, Urs Kanus, Wolfgang Straßer. 185-190
- A Flexible Circuit-Switched NOC for FPGA-Based SystemsClint Hilton, Brent E. Nelson. 191-196
- Energy-Efficient NoC for Best-Effort CommunicationPascal T. Wolkotte, Gerard J. M. Smit, Jens E. Becker. 197-202
- Fault-Tolerant XGFT Network-On-Chip for Multi-Processor System-on-Chip CircuitsHeikki Kariniemi, Jari Nurmi. 203-210
- Modular Partial Reconfiguration in Virtex FPGAsN. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght. 211-216
- Configuration Merging for Adaptive Computer ApplicationsNico Kasprzyk, Jan van der Veen, Andreas Koch. 217-222
- Context Saving and Restoring for Multitasking in Reconfigurable SystemsHeiko Kalte, Mario Porrmann. 223-228
- An FPGA Application with High Speed Serial Transceiver Running at Sub-nominal RateDusan Suvakovic, Ilija Hadzic. 229-234
- FPGA-based implementation and comparison of recursive and iterative algorithmsValery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel. 235-240
- Configurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGAMarc Bautista-Palacios, Luis Baldez, Jordi Sempere-Agulló, Atilà Herms-Berenguer, Francisco Cardells-Tormo, Pep-Lluis Molinet. 241-246
- Defect Tolerance in Multiple-FPGA SystemsZohair Hyder, John Wawrzynek. 247-254
- Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield EnhancementAnthony J. Yu, Guy G. Lemieux. 255-262
- Heterogeneity Exploration for Multiple 2D Filter DesignsChristos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides. 263-268
- Highly Automated FPGA Synthesis of Application-Specific Protocol ProcessorsSeppo Virtanen, Dragos Truscan, Jani Paakkulainen, Jouni Isoaho, Johan Lilius. 269-274
- Ziggurat-based Hardware Gaussian Random Number GeneratorGuanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk. 275-280
- Snow 2.0 IP Core for Trusted HardwareWenhai Fang, Thomas Johansson, Lambert Spaanenburg. 281-286
- A Novel Asynchronous FPGA Architecture Design and Its Performance EvaluationXin Jia, Ranga Vemuri. 287-292
- A Programmable Logic Architecture for Prototyping Clockless CircuitsLaurent Fesquet, Marc Renaudin. 293-298
- GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chipsJerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin. 299-304
- A Verilog RTL Synthesis Tool for Heterogeneous FPGAsPeter Jamieson, Jonathan Rose. 305-310
- Compilation and Management of Phase-Optimized Reconfigurable SystemsHenry Styles, Wayne Luk. 311-316
- Trident: An FPGA Compiler Framework for Floating-Point AlgorithmsJustin L. Tripp, Kristopher D. Peterson, Christine Ahrens, Jeffrey D. Poznanovic, Maya Gokhale. 317-322
- FPGA-Accelerated Reconstruction of Gene Regulatory NetworksIosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides. 323-328
- Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular AutomataPeter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner. 329-334
- A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular AutomataPeter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner. 335-340
- An Analytical Approach to Generation and Exploration of Reconfigurable ArchitecturesAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. 341-346
- An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration?Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa. 347-352
- Cluster Architecture for Reconfigurable Signal Processing Engine for Wireless CommunicationMiyoshi Saito, Hisanori Fujisawa, Nobuo Ujiie, Hideki Yoshizawa. 353-359
- Communication Synthesis in a multiprocessor environmentClaudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere. 360-365
- PGR: A Software Package for Reconfigurable Super-ComputingTsuyoshi Hamada, Naohito Nakasato. 366-373
- On-Chip Communication Topology Synthesis for a Shared Memory ArchitectureSujan Pandey, Manfred Glesner, Max Mühlhäuser. 374-379
- A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoCOlli Lehtoranta, Erno Salminen, Ari Kulmala, Marko Hännikäinen, Timo D. Hämäläinen. 380-385
- Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysisMichael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber. 386-390
- Memory Efficient Design of an MPEG-4 Video Encoder for FPGAsKristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. Vissers. 391-396
- An Autonomous FPGA-based Emulation System for Fast Fault Tolerant EvaluationCelia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes. 397-402
- On the Reliability Evaluation of SRAM-Based FPGA DesignsOlivier Héron, Talal Arnaout, Hans-Joachim Wunderlich. 403-408
- Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance SchemesNicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko. 409-414
- Fast FPGA Placement using Space-filling CurvePritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy. 415-420
- Hierarchical Placement for Large-scale FPAAI. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson. 421-426
- Architecture-Adaptive Routability-Driven Placement for FPGAsAkshay Sharma, Carl Ebeling, Scott Hauck. 427-432
- Generalizing Square Attack using Side-Channels of an AES Implementation on an FPGAVincent Carlier, Hervé Chabanne, Emmanuelle Dottax, Hervé Pelletier. 433-437
- Real-Time Feature Extraction for High Speed NetworksDavid Nguyen, Gokhan Memik, Seda Ogrenci Memik, Alok N. Choudhary. 438-443
- Bitwise Optimised CAM for Network Intrusion Detection SystemsSherif Yusuf, Wayne Luk. 444-449
- High Speed / Low Power Architectures for the Finite Radon TransformShrutisagar Chandrasekaran, Abbes Amira. 450-455
- Towards a Reconfigurable Tracking SystemSebastien Wong, Mark Jasiunas, David A. Kearney. 456-462
- High Performance Stereo Computation ArchitectureJavier Díaz, Eduardo Ros, Sonia Mota, Eva M. Ortigosa, Begoña del Pino. 463-498
- An Emulation Model for Sequential ATPG-Based Bounded Model CheckingQiang Qiang, Daniel G. Saab, Jacob A. Abraham. 469-474
- Accelerating Molecular Dynamics Simulations With Configurable CircuitsYongfeng Gu, Tom Van Court, Martin C. Herbordt. 475-480
- A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital CircuitsVictor Gonçalves, José T. de Sousa, Fernando M. Gonçalves. 481-486
- An FPGA-based Soft Multiprocessor System for IPv4 Packet ForwardingKaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer. 487-492
- Snort Offloader: A Reconfigurable Hardware NIDS FilterHaoyu Song, Todd S. Sproull, Michael Attig, John W. Lockwood. 493-498
- HAIL: A Hardware-Accelerated Algorithm for Language IdentificationCharles M. Kastner, G. Adam Covington, Andrew A. Levine, John W. Lockwood. 499-504
- A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and TestRawat Siripokarpirom. 505-508
- A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video CodingSinan Yalcin, Hasan F. Ates, Ilker Hamzaoglu. 509-514
- Statistical Power Estimation for FPGAElias Todorovich, F. Angarita, Javier Valls, Eduardo I. Boemo. 515-518
- CPU-independent Assembler in an FPGAGeorg Acher, Rainer Buchty, Carsten Trinitis. 519-522
- Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics SystemCarlos Leong, P. Bento, Pedro Rodrigues, Andreia Trindade, J. C. Silva, Pedro Lousã, Joel Rego, J. Nobre, João Varela, João Paulo Teixeira, Isabel C. Teixeira. 523-526
- Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAsRonald Hecht, Stephan Kubisch, Andreas Herrholtz, Dirk Timmermann. 527-530
- Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter BanksAntonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz. 531-534
- Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear CoordinatesF. Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls. 535-538
- Efficient Hardware Architectures for Modular Multiplication on FPGAsDavid Narh Amanor, Viktor Bunimov, Christof Paar, Jan Pelzl, Manfred Schimmler. 539-542
- Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing NodesJawad Khan, Ranga Vemuri. 543-546
- FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked ApproachJosé-Javier Martínez, F. Javier Toledo, F. Javier Garrigós, José Manuel Ferrández de Vicente. 547-550
- Optimization of Start-Up Time and Quiescent Power Consumption of FPGAsArtur Schiefer, Udo Kebschull. 551-554
- QPF: Efficient Quadratic Placement for FPGAsYonghong Xu, Mohammed A. S. Khalid. 555-558
- Safe PLD-based Programmable ControllersJacobo Alvarez, Jorge Marcos, Santiago Fernandez. 559-562
- Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable ArchitecturesJuanjo Noguera, Rosa M. Badia. 563-567
- A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable HardwareKlaus Danne, Marco Platzner. 568-573
- A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGAYasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano. 574-577
- Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image ProcessingFrancisco Cardells-Tormo, Pep-Lluis Molinet, Jordi Sempere-Agulló, Luis Baldez, Marc Bautista-Palacios. 578-581
- Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network ProcessorMartin J. Pearson, Chris Melhuish, Anthony G. Pipe, Mokhtar Nibouche, Ian Gilhespy, Kevin N. Gurney, Benjamin Mitchinson. 582-585
- Evaluation Strategies for Coarse Grained Reconfigurable ArchitecturesHendrik Lange, Hartmut Schröder. 586-589
- Figaro - An Automatic Tool Flow for Designs with Dynamic ReconfigurationKelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl. 590-593
- FPGA Implementation of a GF(2:::4M:::) Multiplier for use in Pairing Based CryptosystemsMaurice Keller, Tim Kerins, William P. Marnane. 594-597
- FPGA s Middleware for Software Defined Radio ApplicationsXavier Revés, Vuk Marojevic, Ramon Ferrús, Antoni Gelonch. 598-601
- Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA DevicesDragomir Milojevic. 602-605
- Integration of a NoC-Based Multimedia Processing PlatformTapani Ahonen, Jari Nurmi. 606-611
- LAMP: A Tool Suite for Families of FPGA-Based Application AcceleratorsTom Van Court, Martin C. Herbordt. 612-617
- Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia ApplicationsSajid Baloch, Imran Ahmed, Tughrul Arslan, Adrian Stoica. 618-621
- Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable ArchitectureBingfeng Mei, Francisco-Javier Veredas, Bart Masschelein. 622-625
- Parameterized Logic Power Consumption Models for FPGA based SystemsJonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides. 626-629
- Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCsGrigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis. 630-635
- A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAsUsama Malik, Oliver Diessel. 636-639
- A Novel Toolset for the Development of FPGA-like Reconfigurable LogicAlexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki. 640-643
- A Reconfigurable Perfect-Hashing Scheme for Packet InspectionIoannis Sourdis, Dionisios N. Pnevmatikatos, Stephan Wong, Stamatis Vassiliadis. 644-647
- An Efficient Approach to Hide the Run-Time Reconfiguration from SW ApplicationsYang Qu, Juha-Pekka Soininen, Jari Nurmi. 648-653
- An FPGA Network Architecture for Accelerating 3DES - CBCChin Mun Wee, Peter R. Sutton, Neil W. Bergmann. 654-657
- An Integrated Framework for Architecture Level Exploration of Reconfigurable PlatformK. Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis. 658-661
- Coping With Uncertainty in FPGA Architecture DesignBoris Ratchev, Mike Hutton, David Mendel. 662-665
- Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGANaoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri. 666-669
- Finite Field Division ImplementationJean-Pierre Deschamps, Gustavo Sutter. 670-674
- FPGA-Aware Garbage Collection in JavaPhilippe Faes, Mark Christiaens, Dries Buytaert, Dirk Stroobandt. 675-680
- High-Throughput Reconfigurable Computing: A Design Study of an IDEA Encryption Cryptosystem on the SRC-6e Reconfigurable ComputerAllen Michalski, Kris Gaj, Duncan A. Buell. 681-686
- Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGANicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli. 687-690
- Mullet - A Parallel Multiplier GeneratorKuen Hung Tsoi, Philip Heng Wai Leong. 691-694
- NetFlow Probe Intended for High-Speed NetworksMartin Zádník, Tomas Pecenka, Jan Korenek. 695-698
- Performance Tuning of Iterative Algorithms in Signal ProcessingZdenek Pohl, Premysl Sucha, Jiri Kadlec, Zdenek Hanzálek. 699-702
- Run-Time Scheduling for Random Multi-Tasking in Reconfigurable CoprocessorsPascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon. 703-706
- A Low-Energy FPGA: Architecture Design and Software-Supported Design FlowK. Siozios, Dimitrios Soudris, Adonios Thanailakis. 707-708
- A Power-Performance Scalable FPGA Using Configurable Voltage Domains and Design Mapping ToolFrank Honoré. 709-710
- An Approach to Scalable Molecular Dynamics Simulation Using Supercomputing Adaptive Processing ElementsLuis E. Cordova, Duncan A. Buell. 711-712
- Computer Arithmetic Synthesis Technologies on Reconfigurable PlatformsKuen Hung Tsoi. 713-714
- Dual FiXed-point : An Efficient Alternative to Floating-point Computation for DSP applicationsChun Te Ewe. 715-716
- Efficient Execution on Reconfigurable Devices Using Concepts of PipeliningFlorian Dittmann. 717-718
- Exploration of Heterogeneous Reconfigurable ArchitecturesAlastair M. Smith. 719-720
- FPGA Finite-Difference Time-Domain solver for thermal simulationFernando Pardo, P. López, Diego Cabello, M. Balsi. 721-722
- FPGA Implementation of an Augmented Reality Application for Visually Impaired PeopleF. Javier Toledo, José-Javier Martínez, F. Javier Garrigós, José Manuel Ferrández de Vicente. 723-724
- FPGA Interconnect Fault toleranceNicola Campregher. 725-726
- Hardware Emulation of a Network on Chip Architecture based on a Clockwork Routed Manhattan Street NetworkKurian Oommen, David Harle. 727-728
- Instruction Set Extension Using Microblaze ProcessorJános Lazányi. 729-730
- Leveraging Reconfigurability in the Design ProcessLesley Shannon, Paul Chow. 731-732
- MechanoProcessor: Modelling the Rodent Whisker Sensory System using FPGAMartin J. Pearson. 733-734
- Next Generation Architectures and CAD for Power Aware Programmable FabricsRajarshee P. Bharadwaj. 735-738
- PAHLS: Towards Run-Time Synthesis for FPGAsRenqiu Huang, Ranga Vemuri. 739-740
- Reconfigurable Architectures for Real-Time Network Anomaly DetectionDavid Nguyen. 741-742
- Requested-QoS Driven Runtime Reconfiguration of Mobile DevicesHiren Joshi, S. S. Verma, G. K. Sharma. 743-744
- Design of a Dynamic Reconfigurable Multi-Grained Hardware Architecture with Adaptive Runtime RoutingAlexander Thomas. 745-746
- Testing Superscalar Processors in Functional ModeVirendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara. 747-750