Abstract is missing.
- Low Power Memory Architectures for Video ApplicationsBhanu Kapoor. 2-6 [doi]
- Reducing Power Consumption of Dedicated Processors Through Instruction Set EncodingLuca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino. 8-12 [doi]
- A Low-Power High-Performance Embedded SRAM MacrocellA. M. Fahim, Muhammad M. Khellah, Mohamed I. Elmasry. 13-17 [doi]
- Low-Power Design of Finite Field Multipliers for Wireless ApplicationsAmr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasry. 19-25 [doi]
- Guidelines for Use of Registers and Multiplexers in Low Power Low Voltage DSP SystemsDusan Suvakovic, C. Andre T. Salama. 26-29 [doi]
- A Bootstrapped NMOS Charge Recovery LogicSeung-Moon Yoo, Seung-Moon Kang. 30-33 [doi]
- Power Reducing Techniques for Clocked CMOS PLAsRichard F. Hobson. 34-38 [doi]
- Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission LinesYehea I. Ismail, Eby G. Friedman, José Luis Neves. 39-44 [doi]
- A New Full Adder Cell for Low-Power ApplicationsAhmed M. Shams, Magdy A. Bayoumi. 45 [doi]
- beta-Driven Threshold ElementsVictor Varshavsky. 52-58 [doi]
- A VLSI High-Performance Encoder with Priority LookaheadJosé G. Delgado-Frias, Jabulani Nyathi. 59-64 [doi]
- Noise Margins of Threshold Logic Gates containing Resonant Tunneling DiodesMayukh Bhattacharya, Pinaki Mazumder. 65-70 [doi]
- 600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication ApplicationsAzman M. Yusof, Lim Chu Aun, S. M. Rezaul Hasan. 71-76 [doi]
- Stability of a Continuous-Time State Variable Filter with OP-AMP and OTA-C IntegratorsTim Bakken, John Choma Jr.. 77-82 [doi]
- Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked LogicI. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis. 83-88 [doi]
- CMOS Tapered Buffer Design for Small Width Clock/Data Signal PropagationJoão Navarro Jr., Wilhelmus A. M. Van Noije. 89-94 [doi]
- Design of Clock Distribution Networks in Presence of Process VariationsMohamed Nekili, Yvon Savaria, Guy Bois. 95-102 [doi]
- Design of an 8: 1 MUX at 1.7Gbit/s in 0.8?I m CMOS TechnologyJoão Navarro Jr., Wilhelmus A. M. Van Noije. 103-107 [doi]
- Issues in the Design of Domino Logic CircuitsPranjal Srivastava, Andrew Pua, Larry Welch. 108-112 [doi]
- A Novel 1.5-V Cmos MixerGianluca Giustolisi, Giovanni Palmisano, Gaetano Palumbo, C. Strano. 113-117 [doi]
- Analysis of Adaptive CMOS Down Conversion MixersCan K. Sandalci, Sayfe Kiaei. 118-121 [doi]
- Artificial Neural Network Electronic Nose for Volatile Organic CompoundsHoda S. Abdel-Aty-Zohdy. 122 [doi]
- A VLSI Self-Compacting Buffer for DAMQ Communication SwitchesJosé G. Delgado-Frias, Richard Diaz. 128-133 [doi]
- A Dictionary Machine Emulation on a VLSI Computing Tree SystemAdger E. Harvin III, José G. Delgado-Frias. 134-139 [doi]
- Modeling and Analysis of The Difference-Bit CacheAshutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John. 140-145 [doi]
- Modeling of Shift Register-based ATM SwitchSandeep Agarwal, Fayez El Guibaly. 146-151 [doi]
- An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth RequirementJen-Chien Tuan, Chein-Wei Jen. 152-156 [doi]
- MPEG-2 Video Decoder for DVDNien-Tsu Wang, Chen-Wei Shih, Duan Juat Wong-Ho, Nam Ling. 157-160 [doi]
- A Self Timed Asynchronous Router for an Heterogeneous Parallel MachineEric Senn, Bertrand Zavidovique. 161-167 [doi]
- Non-Refreshing Analog Neural Storage Tailored for On-Chip LearningBassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi. 168 [doi]
- Residue to Binary Number Converters for (2:::n:::-1, 2:::n:::, 2:::n:::+1)Yuke Wang, Xiaoyu Song, El Mostapha Aboulhamid. 174-178 [doi]
- The Design of Residue Number System Arithmetic Units for A VLSI Adaptive EqualizerInseop Lee, W. Kenneth Jenkins. 179-184 [doi]
- An Efficient Residue to Weighted Converter for a New Residue Number SystemAlexander Skavantzos. 185-191 [doi]
- The Chinese Abacus Method: Can We Use It for Digital Arithmetic?Franco Maloberti, Chen Gang. 192-195 [doi]
- Merged Arithmetic for Computing Wavelet TransformsGwangwoo Choe, Earl E. Swartzlander Jr.. 196-201 [doi]
- Digital Arithmetic Using Analog ArraysSaeid Sadeghi-Emamchaie, Graham A. Jullien, Vassil S. Dimitrov, William C. Miller. 202-207 [doi]
- A Combined Interval and Floating Point MultiplierJames E. Stine, Michael J. Schulte. 208 [doi]
- Test Compaction for Synchronous Sequential Circuits by Test Sequence RecyclingIrith Pomeranz, Sudhakar M. Reddy. 216-221 [doi]
- Random Self-Test Method - Applications on PowerPC (tm) Microprocessor CachesRajesh Raina, Robert F. Molyneaux. 222-229 [doi]
- A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault DetectionB. Provost, E. Sanchez-Sinencio, Anna Maria Brosa. 230-236 [doi]
- VHDL Testability Analysis Based on Fault Clustering and Implicit Fault InjectionF. S. Bietti, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto. 237-242 [doi]
- IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS CircuitsHendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy. 243-248 [doi]
- A Design-for-Testability Technique for Detecting Delay Faults in Logic CircuitsKaamran Raahemifar, Majid Ahmadi. 249 [doi]
- Development of a CMOS Cell Library for RF Wireless and Telecommunications ApplicationsRobert H. Caverly. 258-263 [doi]
- Design Issues of LC Tuned Oscillators for Integrated TransceiversCarlo Samori, Andrea L. Lacaita, Alfio Zanchi, P. Vita. 264-269 [doi]
- Novel Simple Models Of Cml Propagation DelayMassimo Alioto, Gaetano Palumbo. 270-274 [doi]
- Next-Generation Narrowband RF Front-Ends in Silicon IC TechnologyJohn R. Long. 275-280 [doi]
- Low Voltage Low power CMOS AGC circuit for wireless communicationHassan O. Elwan, Mohammed Ismail. 281-285 [doi]
- A Continuous-Time Switched-Current Sigma-Delta Modulator with Reduced Loop DelayLouis Luh, John Choma Jr., Jeffrey T. Draper. 286 [doi]
- An Exact Input Encoding Algorithm for BDDs Representing FSMsWilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha. 294-300 [doi]
- Maximum Current Estimation in Programmable Logic ArraysSudhakar Bobba, Ibrahim N. Hajj. 301-306 [doi]
- Mutually Disjoint Signals and Probability Calculation in Digital CircuitsVishwani D. Agrawal, Sharad C. Seth. 307-312 [doi]
- Identifying High-Level Components in Combinational CircuitsTravis E. Doom, Jennifer L. White, Anthony S. Wojcik, Gregory H. Chisholm. 313-318 [doi]
- Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical ConstraintsAnthony D. Johnson. 319-324 [doi]
- Linear Transformations and Exact Minimization of BDDsWolfgang Günther, Rolf Drechsler. 325-330 [doi]
- Timed Supersetting and the Synthesis of Telescopic UnitsLuca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino. 331-337 [doi]
- Tabu Search Based Circuit OptimizationSadiq M. Sait, Habib Youssef, Munir M. Zahra. 338-343 [doi]
- On the Characterization of Multi-Point Nets in Electronic DesignsDirk Stroobandt, Fadi J. Kurdahi. 344 [doi]
- HOOVER: Hardware Object-Oriented VerificationMostafa M. Aref, Khaled M. Elleithy. 351-355 [doi]
- MDG-based Verification by Retiming and Combinational TransformationsOtmane Aït Mohamed, Eduard Cerny, Xiaoyu Song. 356-361 [doi]
- Practical Considerations in Formal Equivalence Checking of PowerPC(tm) MicroprocessorsArun Chandra, Li-C. Wang, Magdy S. Abadir. 362-367 [doi]
- Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VISJianping Lu, Sofiène Tahar. 368 [doi]
- Performance Optimization of Self-Timed CircuitsMark A. Franklin, Prithvi Prabhu. 374-379 [doi]
- Stochastic Evolution Algorithm For Technology MappingAhmad S. Al-Mulhem, Alaaeldin Amin, Habib Youssef. 380-385 [doi]
- RCRS: A Framework for Loop Scheduling with Limited Number of RegistersKaisheng Wang, Ted Zhihong Yu, Edwin Hsing-Mean Sha. 386-391 [doi]
- A Quantitative Study of the Benefits of Area-I/O in FPGAsHerwig Van Marck, Jo Depreitere, Dirk Stroobandt, Jan Van Campenhout. 392-399 [doi]
- Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder ExampleDale E. Hocevar, Ching Yu Hung, Dan Pickens, Sundararajan Sriram. 400 [doi]
- Low Power Driven Scheduling and BindingJim E. Crenshaw, Majid Sarrafzadeh. 406-413 [doi]
- Effective Capacitance Macro-Modelling for Architectural-Level Power EstimationMuhammad M. Khellah, Mohamed I. Elmasry. 414-419 [doi]
- A Methodology for High Level Power Estimation and ExplorationVamsi Krishna, N. Ranganathan. 420-425 [doi]
- How to Transform an Architectural Synthesis Tool for Low Power VLSI DesignsS. Gailhard, Nathalie Julien, Jean-Philippe Diguet, Eric Martin. 426 [doi]
- Sharing Electronic Design Data Via Semantic SpacesKaren C. Davis, Satish Venkatesan, Lois M. L. Delcambre. 432-439 [doi]
- VHDL-based EDA Tool Implementation with JavaRick Miller. 440-445 [doi]
- Standard Data Representations for VLSI Algorithm DevelopmentDavid Hertweck, Mihaela Nica, Sang-Eon Park, Carla N. Purdy. 446-451 [doi]
- A Storage Structure for Graph-Oriented Databases Using an Array of Element TypesTeruhisa Hochin, Tatsuo Tsuji. 452 [doi]