Table of Contents

• How to Design a Parallel ComputerDavid May. 2
• Liquid Nitrogen CMOS for Computer ApplicationsFritz H. Gaensslen, David D. Meyer. 4-8
• Neural Networks UpdateE. Scott Kirkpatrick. 10
• Design and Test-The Two Sides of a CoinVishwani D. Agrawal. 12
• Logic Design for a High Performance Mainframe Computer, The HITAC M-880 ProcessorYooichi Shintani, Kiyoshi Inoue, Toru Shonai, K. Wada, S. Abe, Katsuro Wakai. 14-20
• Architectural Considerations for SF-core Based MicroprocessorA. Shacham, Y. Levy, Z. Bronstein, E. Loewenstein, D. M. Bruck, D. Deitcher. 21-24
• Module Generation for AND/XOR Fields (XPLAs)Juergen Froessl, Bernhard Eschermann. 26-29
• A Layout Compaction Algorithm with Multiple Grid ConstraintsJin-fuw Lee. 30-33
• Methods and Algorithms for Converting IC Designs Between Incompatible Design SystemsEero Pajarre, Tapani Ritoniemi, Hannu Tenhunen. 34-37
• Incremental Synthesis for Engineering ChangesYosinori Watanabe, Robert K. Brayton. 40-43
• Concurrent Resynthesis for Network OptimizationKuang-Chien Chen, Masahiro Fujita. 44-48
• Dual Global FlowRobert F. Damiano, Len Berman. 49-53
• Stafan Algorithms for MOS CircuitsJoan Villoldo, Prathima Agrawal, Vishwani D. Agrawal. 56-59
• Fast Differential Fault Simulation by Dynamic Fault OrderingGianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda. 60-63
• A Fine Grain Architecture for Parallel Fault SimulationJohn A. Trotter, Richard Evans. 64-67
• Partitioning Sequential Circuits for Logic OptimizationSujit Dey, Franc Brglez, Gershon Kedem. 70-76
• Redundancy Identification and Removal Based on Implicit State EnumerationHyunwoo Cho, Gary D. Hachtel, Fabio Somenzi. 77-80
• Implicit Manipulation of Equivalence Classes Using Binary Decision DiagramsBill Lin, A. Richard Newton. 81-85
• Retiming of Circuits with Single Phase Transparent LatchesNarendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 86-89
• Modeling fo Interconnections Lines for Stimulation of VLSI CircuitsF. Sebastiã G. dos Santos, Jacobus W. Swart. 92-95
• PowerPlay-Fast Dynamic Power Estimation Based on Logic SimulationThomas H. Krodel. 96-100
• Parallel Event-Driven Waveform RelaxationYen-Cheng Wen, Kyle Gallivan, Resve A. Saleh. 101-104
• A Technique for Generating Efficient SimulatorsPrzemyslaw Bakowski, Jean-Luc Dubois, Adam Pawlak. 105-108
• Designing Self-Testable Cellular ArraysCheng-Wen Wu, Shyue-Kung Lu. 110-113
• Concurrent Error Detection in Array Dividers by Alternating Input DataChin-Long Wey. 114-117
• Testing of Analog Neural Array-Processor ChipsWen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda. 118-121
• Fault-Tolerant Model of Neural ComputingLon-Chan Chu. 122-125
• On-Chip Multiple Superscalar Processors with Secondary Cache MemoriesM. Hanawa, Tadahiko Nishimukai, O. Nishii, M. Suzuki, K. Yano, M. Hiraki, S. Shukuri, T. Nishida. 128-131
• System Level ASIC Design for Hewleet-Packard s Low Cost PA-RISC WorkstationsLeith Johnson, Rob Horning, Larry Thayer, Daniel Li, Rob Snyder. 132-135
• DesignFab: A Methodology for ULSI Microprocessor DesignMoshe Shahaf. 136-139
• Implementation-Independent Model of an Instruction Set Architecture Using VHDLMaximo H. Salinas, Barry W. Johnson, James H. Aylor. 140-145
• Fuzzy Logic: Why the U.S. Falls Behind?George J. Klir. 148
• Overview of the Monsoon ProjectKenneth R. Traub, Gregory M. Papadopoulos, Michael J. Beckerle, James E. Hicks, Jonathan Young. 150-155
• The Monsoon Interconnection NetworkChristopher F. Joerg, G. Andrew Boughton. 156-159
• Test and Validation for Monsoon Processing ElementsMichael J. Beckerle, Gregory M. Papadopoulos. 160-163
• An Effective Analog Approach to Steiner RoutingAndrew B. Kahng. 166-169
• Performance-Driven Global Routing for Cell Based ICsJason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong. 170-173
• Critical Net RoutingJames P. Cohoon, L. J. Randall. 174-177
• Synthesis of Delay-Insensitive Circuits by Refinements into Atomic ThreadsHon F. Li, S. C. Leung, P. N. Lam. 180-186
• Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)Mark E. Dean, David L. Dill, Mark Horowitz. 187-191
• Synthesis of Asynchronous State Machines Using A Local ClockSteven M. Nowick, David L. Dill. 192-197
• Amdahl Chip Delay Test SystemI. Deol, Chittaranjan Mallipeddi, T. Ramakrishnan. 200-205
• Robust Path Delay-Fault Testability on Dynamic CMOS CircuitsPatrick C. McGeer. 206-211
• Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow GraphsAbhijit Chatterjee, Manuel A. d Abreu. 212-215
• A Data-Driven Architecture for Distributed Parallel ProcessingToshiyuki Tamura, Shinji Komori, Fumiyasu Asai, Hirono Tsubota, Hisakazu Sato, Hidehiro Takata, Yoshihiro Seguchi, Takeshi Tokuda, Hiroaki Terada. 218-224
• MPU: A N-Tuple Matching ProcessorRobert H. Payne, José G. Delgado-Frias. 225-228
• Transitive Closure and Graph Component Labeling on Realistic Processor Arrays Based on Reconfigurable Mesh NetworkMassimo Maresca, Pierpaolo Baglietto. 229-232
• Decomposed Arbiters for Large Crossbars with Multi-Queue Input BuffersHsin-Chou Chi, Yuval Tamir. 233-238
• A Compositional Transformation for Formal VerificationEduard Cerny. 240-244
• Automatic Derivation of FSM Specification to Implementation EncodingCarl Pixley, Gary Beihl, Ernesto Pacas-Skewes. 245-249
• Design Verfication and Reachability Analysis Using Algebraic ManipulationSrinivas Devadas, Kurt Keutzer, A. S. Krishnakumar. 250-258
• Boolean Satisfiability and Equivalence Checking Using General Binary Decision DiagramsPranav Ashar, Abhijit Ghosh, Srinivas Devadas. 259-264
• Power-Down Structures for BISTPaul S. Levy. 266-269
• A Unique Approach to Built-in-Self-Test Circuit DesignSami A. Al-Arian, Hussam Y. Abujbara, Jim C. Ruel. 270-274
• New Implementations, Tools, and Experiments for Decreasing Self-Checking PLAs Area OverheadMichael Nicolaidis, M. Boudjit. 275-281
• A Built-In Self-Testing Approach for Minimizing Hardware OverheadScott Chiu, Christos A. Papachristou. 282-285
• CMOS Processor Circuit Design in Hewlett-Packard s Series 700 WorkstationsCraig Gleason, Mark Forsyth, Charlie Kohlhardt, Steve Mangelsdorf, Barry Arnold, Rick Luebs. 288-292
• F-RISC/I: Fast Reduced Instruction Set Computer with GaAs (H)MESFET ImplementationC. K. Tien, C. C. Poon, Hans J. Greub, Jack F. McDonald. 293-296
• F-RISC/G: AlGaAs/GaAs HBT Standard Cell LibraryK. Nah, Robert F. Philhower, J. S. Van Etten, S. Simmons, V. Tsinker, James Loy, Hans J. Greub, Jack F. McDonald. 297-300
• A Mechanism for Efficient Context SwitchingPeter R. Nuth, William J. Dally. 301-304
• A Genetic Algorithm for Global Improvement of Macrocell LayoutsK. Glasmacher, A. Hess, Gerhard Zimmermann. 306-313
• I/O Pad Assignment Based on the Circuit StructureMassoud Pedram, Kamal Chaudhary, Ernest S. Kuh. 314-318
• A Provable Near-Optimal Algorithm for the Channel Pin Assignment ProblemJason Cong, Kei-Yong Khoo. 319-322
• Design Methodology for a MIPS Compatible Embedded Control ProcessorRaymond Peck, Jay Patel. 324-328
• Verification Techniques for a MIPS Compatibvle Embedded Control ProcessorDarren Jones, Rongken Yang, Mark Kwong, George Harper. 329-332
• The Architecture of the LR33000: A MIPS Compatible RISC Processor for Embedded Control ApplicationsBob Culk, Sanjay Desai, Moshe Gavrielov, George Harper, Darren Jones, Mark Kwong, Marlon Murzello, Tim Oke, Jay Patel, Raymond Peck, James Wei, Rongken Yang. 333-336
• Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-IIMark Genoe, Luc J. M. Claesen, Eric Verlind, Frank Proesmans, Hugo De Man. 338-341
• Specifying System Behavior in CPAMichael C. McFarland, Thaddeus J. Kowalski. 342-345
• A Formally Verified System for Logic SynthesisMark Aagaard, Miriam Leeser. 346-350
• Aliasing Probability in Multiple Input Linear Signature Automata for Q-ary Symmetric ErrorsGeetani Edirisooriya, John P. Robinson. 352-355
• Reduced Hamming Count and Its Aliasing ProbabilityAnita Gleason, Wen-Ben Jone. 356-359
• On the Manisfestation of Faults to Errors in Signature AnalysisJohn C. Chan, Baxter F. Womack, D. F. Wong. 360-363
• Operation Method in Fuzzy Set Operation ProcessorAtsushi Katsumata, Hidekazu Tokunaga, Seiji Yasunobu. 366-369
• A Tag Coprocessor Architecture for Symbolic LanguagesVicente Fuentes-Sánchez, Peter Y. K. Cheung. 370-373
• An Efficient Pattern Match Architecture for Production Systems Using Content-Addressable MemoryChie Dou, Shao-Ming Wu. 374-378
• Object-Caching for Performance in Object-Oriented SystemsJ. Morris Chang, Edward F. Gehringer. 379-385
• Early Performance Estimation of Super Scalar Machine ModelsPradip Bose. 388-392
• Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound SorterSankaran Karthik, Indira de Souza, Joseph T. Rahmeh, Jacob A. Abraham. 393-396
• An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor ReconfigurationPeter M. Athanas, Harvey F. Silverman. 397-400
• FASTCHART-Idea and ImplementationLennart Lindh, Frank Stanischewski. 401-404
• Mapping Design Knowledge from Multiple RepresentationsWalling R. Cyre. 406-409
• Synthesizing Converters Between Finite State ProtocolsJanaki Akella, Kenneth L. McMillan. 410-413
• An Integrated Design Environment for Application Specific Integrated ProcessorJun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi. 414-417
• Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level SynthesisChien-In Henry Chen. 418-421
• Random Testability of Redundant CircuitsAndrzej Krasniewski, Alexander Albicki. 424-427
• Logic Synthesis of 100-percent Testable Logic NetworksGert-Jan Tromp, A. J. van de Goor. 428-431
• Fault Tolerant VLSI Design with Functional Block RedundancyRolf Ernst, P. Nowottnick. 432-436
• Design and Test Automation-Gigascale Integration (GSI) in the 21st CenturyJames D. Meindl. 438
• IBM AS/400 Processor Architecture and Design MethodologyQuentin G. Schmierer, Andrew H. Wottreng. 440-443
• VLSI Design Automation for the Application System/400Robert F. Lembach, John M. Borkenhagen, John R. Elliott, Randall A. Schmidt. 444-447
• IBM AS/400 Processor TechnologyDennis T. Cox, Charles L. Johnson, Bruce G. Rudolph, David W. Siljenberg, Robert R. Williams. 448-452
• Logic Synthesis of Synchronous Parallel ControllersJames Pardey, Martin Bolton. 454-457
• SYNTEST: A Method for High-Level SYNthesis with Self-TESTabilityChristos A. Papachristou, Scott Chiu, Haidar Harmanani. 458-462
• Accessibility Analysis on Data Flow Graph: An Approach to Design for TestabilityChung-Hsing Chen, Chienwen Wu, Daniel G. Saab. 463-466
• Fine-Line Printed Circuit Board for High-Performance Computer DesignChi-Chai Huang, John Willis, Tim Schmitt. 468-471
• Design Considerations for Digital Circuit Interconnections in a Multilayer Printed Circuit BoardAmit P. Agrawal, Chi Shih Chang, Debra A. Gernhart. 472-478
• Fast Capacitance Extraction of General Three-Dimensional StructuresKeith Nabors, S. Kim, Jacob White, Stephen D. Senturia. 479-484
• A Simulator for General Purpose Optical ArraysWalter B. Marvin, Wayne Burleson. 486-489
• An Optical Multichip ModuleAlex G. Dickinson, M. M. Downs. 490-493
• A GaAs Receiver Module for Optoelectronic Computing and InterconnectionJoongho Choi, Bing J. Sheu. 494-497
• VLSI Designs for High-Speed Huffman DecoderShih-Fu Chang, David G. Messerschmitt. 500-503
• BioSCAN: A VLSI-Based System for Biosequence AnalysisC. Thomas White, Raj K. Singh, Peter B. Reintjes, Jordan Lampe, Bruce W. Erickson, Wayne D. Dettloff, Vernon L. Chi, Stephen F. Altschul. 504-509
• VLSI Implementation of a New Block CipherH. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai. 510-513
• An Optimal Algorithm for Spiral Floorplan DesignsCheng-Hsi Chen, Ioannis G. Tollis. 516-519
• Area Optimization for Higher Order Hierarchical FloorplansKhe-Sing The, D. F. Wong. 520-523
• The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing OrderSusmita Sur-Kolay, Bhargab B. Bhattacharya. 524-527
• Flipping Modules to Minimize Maximum Wire LengthKyunrak Chong, Sartaj Sahni. 528-531
• High Performance Packaged Electronics for the IBM ES9000:::TM::: MainframeArnold E. Barish, James P. Eckhardt, Mark D. Mayo, Walter A. Svarczkopf, Santosh P. Gaur, Rao R. Tummala. 534-539
• IBM ES/9000:::TM::: System Architecture and HardwareW. J. Nohilly, V. T. Lund. 540-543
• Enhanced Chip/Package Design for the IBM ES/9000:::TM:::R. S. Belanger, David P. Conrady, Philip S. Honsinger, T. J. Lavery, Sara J. Rothman, Erich C. Schanzenbach, D. Sitaram, C. R. Selinger, R. E. DuBois, G. W. Mahoney, G. F. Miceli. 544-549
• Design Automation of Test for the EX/9000:::TM::: Series ProcessorsBrion L. Keller, David A. Haynes. 550-553
• A Comparison of Redundant CORDIC Rotation EnginesJohn A. Harding, Tomás Lang, Jeong-A. Lee. 556-559
• A Fast Division Algorithm for VLSIN. Burgess. 560-563
• High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number RepresentationHosahalli R. Srinivas, Keshab K. Parhi. 564-571
• New Classes of Unidirectional Error-Detecting CodesBehrooz Parhami. 574-577
• Design and Synthesis of Self-Checking VLSI Circuits and SystemsNiraj K. Jha, Sying-Jyan Wang. 578-581
• Design of a Self-Testing Checker for Borden CodeStanislaw J. Piestrak. 582-585
• Technologies for Rapid Prototyping of Multi-Chip ModulesRobert F. Miracky, T. Bishop, Claire T. Galanakis, H. Hashemi, Tom J. Hirsch, S. Madere, Heinrich G. Müller, T. Rudwick, L. Smith, Scott C. Sommerfeldt, B. Weigler. 588-592
• Energy Considerations in Multichip-Module Based MultiprocessorsJames B. Burr, Allen M. Peterson. 593-600
• The Commercial Realization of Multi-Chip Modules Quo VadimusRudi Hendel. 601-605
• High-Performance VLSI Processor for Robot Inverse Dynamics ComputationSomchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi. 608-611
• A New O(n log n) Scheduling Heuristic for Parallel Decomposition of Sparce MatricesRicardo Telichevesky, Prathima Agrawal, John A. Trotter. 612-616
• A Predictive Parallel Motion Estimation Algorithm for Digital Image ProcessingLiang-Gee Chen, Wai-Ting Chen, Yeu-Shen Jehng, Tzi-Dar Chiueh. 617-620
• A Multiprocessor Architecture for Circuit SimulationJohn A. Trotter, Prathima Agrawal. 621-625
• Three-Level Decomposition with Application to PLDsAbdul A. Malik, David Harrison, Robert K. Brayton. 628-633
• An Algorithm for the Multi-Level Minimazation of Reed-Muller RpresentationsJonathan Saul. 634-637
• Identification of Viable Paths Using Binary Decision DiagramsYun-Cheng Ju, Resve A. Saleh. 638-641
• Optimal Clocking of Circular PipelinesKarem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson. 642-650