Abstract is missing.
- System Design: Traditional Concepts and New ParadigmsAlberto Ferrari, Alberto L. Sangiovanni-Vincentelli. 2-13 [doi]
- The MARCO/DARPA Gigascale Silicon Research CenterKurt Keutzer, A. Richard Newton. 14 [doi]
- CAD Techniques for Embedded Systems-on-SiliconWayne Wolf. 24 [doi]
- Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic ProgrammingEduard Cerny, Fen Jin. 32-39 [doi]
- Formal Verification of Synthesized Analog DesignsAbhijit Ghosh, Ranga Vemuri. 40-45 [doi]
- Implicit Verification of Structurally Dissimilar Arithmetic CircuitsTed Stanion. 46-50 [doi]
- Automatic Error Correction of Tri-State CircuitsDirk W. Hoffmann, Thomas Kropf. 51 [doi]
- Design Methodology for a One-Shot Reed-Solomon Encoder and DecoderSumio Morioka, Yasunao Katayama. 60-67 [doi]
- High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-SelectionJae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr.. 68-72 [doi]
- Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in AdditionTomás Lang, Javier D. Bruguera. 73-79 [doi]
- A Unified Method for Iterative Computation of Modular Multiplication and Reduction OperationsWilliam L. Freking, Keshab K. Parhi. 80 [doi]
- Designing the M·CORE:::TM::: M3 CPU ArchitectureJeff Scott, Lea Hwang Lee, Ann Chin, John Arends, Bill Moyer. 94-101 [doi]
- Performance Evaluation of Configurable Hardware Features on the AMD-K5Mike Clark, Lizy Kurian John. 102-107 [doi]
- Detailed Characterization of a Quad Pentium Pro Server Running TPC-DQiang Cao, Josep Torrellas, Pedro Trancoso, Josep-Lluis Larriba-Pey, Bob Knighten, Youjip Won. 108 [doi]
- On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar ProcessorsSrivatsan Srinivasan, Lizy Kurian John. 124-130 [doi]
- Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case StudyWilliam Fornaciari, Donatella Sciuto, Cristina Silvano. 131 [doi]
- A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211Tor E. Jeremiassen. 138-145 [doi]
- Evaluation of Computing in Memory Architectures for Digital Image Processing ApplicationsDavid L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor. 146-151 [doi]
- Customization of a CISC Processor Core for Low-Power ApplicationsYou-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung. 152 [doi]
- A New Weight Set Generation Algorithm for Weighted Random Pattern GenerationHangkyu Lee, Sungho Kang. 160-165 [doi]
- Multiple Paths Sensitization of Digital Oscillation Built-In Self TestChristian Dufaza. 166-174 [doi]
- Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test AlgorithmPaul Chang, Brion L. Keller, Sarala Paliwal. 175 [doi]
- Design and Evaluation of a Selective Compressed Memory SystemJang-Soo Lee, Won-Kee Hong, Shin-Dug Kim. 184-191 [doi]
- FlexRAM: Toward an Advanced Intelligent Memory SystemYi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik. 192-201 [doi]
- ActiveOS: Virtualizing Intelligent MemoryMark Oskin, Frederic T. Chong, Timothy Sherwood. 202 [doi]
- An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian RelaxationI-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou. 210-215 [doi]
- An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAsK. K. Lee, D. F. Wong. 216-221 [doi]
- An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two VoltagesChunhong Chen, Majid Sarrafzadeh. 222 [doi]
- Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power DesignKhurram Muhammad, Dinesh Somasekhar, Kaushik Roy. 230-235 [doi]
- A Regular Layout Structured Multiplier Based on Weighted Carry-Save AddersBong-Il Park, In-Cheol Park, Chong-Min Kyung. 243 [doi]
- A Robust Solution to the Timing Convergence Problem in High-Performance DesignNarendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking. 250-257 [doi]
- Performance Driven Optimization of Network Length in Physical PlacementWilm E. Donath, Prabhakar Kudva, Lakshmi N. Reddy. 258-265 [doi]
- Efficient Crosstalk EstimationMartin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi. 266 [doi]
- A High-Performance Hardware-Efficient Memory Allocation Technique and DesignHasan Cam, Mostafa H. Abd-El-Barr, Sadiq M. Sait. 274-276 [doi]
- Improving Microcontroller Power Consumption through a Segmented Gray Code Program CounterRolf Hakenes, Yiannos Manoli. 277-278 [doi]
- A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific ProcessingKentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada. 279-280 [doi]
- Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code LevelsRamesh Radhakrishnan, Juan Rubio, Lizy Kurian John. 281-284 [doi]
- Automatic Generation of Tree Multipliers Using Placement-Driven NetlistsAvinash K. Gautam, V. Visvanathan, S. K. Nandy. 285-288 [doi]
- Yield Optimization by Design Centering and Worst-Case Distance AnalysisG. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim. 289-290 [doi]
- Area, Performance, and Yield Implications of Redundancy in On-Chip CachesTom Thomas, Brian Anthony. 291-292 [doi]
- Conceptual Modeling and SimulationWalling R. Cyre. 293-296 [doi]
- CalmRISC:::TM:::: A Low Power Microcontroller with Efficient Coprocessor InterfaceKyoung-Mook Lim, Seh-Woong Jeong, Yong-Chun Kim, Seung-Jae Jeong, Hong-Kyu Kim, Yang-Ho Kim, Bong-Young Chung, Hyung-Lae Roh, H. S. Yang. 299-302 [doi]
- An Even Wiring Approach to the Ball Grid Array Package RoutingShuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai. 303-306 [doi]
- Synthesis of Pseudo Kronecker Lattice DiagramsPer Lindgren, Rolf Drechsler, Bernd Becker. 307-310 [doi]
- Generic Universal Switch BlocksMichael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang. 311-314 [doi]
- Multi-Level Logic Minimization through Fault Dictionary AnalysisRonald W. Mehler, M. Ray Mercer. 315-318 [doi]
- A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology MappingKang Yi, Seong Yong Ohm. 319-320 [doi]
- Novel Formulations for Low-Power Binding of Function Units in High-Level SynthesisAshok Kumar, Magdy A. Bayoumi. 321-324 [doi]
- An Efficient Functional Coverage Test for HDL Descriptions at RTLChien-Nan Jimmy Liu, Jing-Yang Jou. 325-327 [doi]
- An Efficient Interconnect Test Using BIST Module in a Boundary-Scan EnvironmentHyunjin Kim, Jongchul Shin, Sungho Kang. 328-329 [doi]
- On-Line BIST for Testing Analog CircuitsJaime Velasco-Medina, Iyad Rayane, Michael Nicolaidis. 330 [doi]
- An Environment for Exploring Low Power Memory Configurations in System Level DesignSari L. Coumeri, Donald E. Thomas. 348-353 [doi]
- Architectural Synthesis of Timed Asynchronous SystemsBrandon M. Bachman, Hao Zheng, Chris J. Myers. 354-363 [doi]
- Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CADHen-Ming Lin, Jing-Yang Jou. 364 [doi]
- A Compiler-Assisted Data Prefetch ControllerSteven P. Vanderwiel, David J. Lilja. 372-377 [doi]
- Energy and Performance Improvements in Microprocessor Design Using a Loop CacheNikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis. 378-383 [doi]
- A Fast Median Filter Using AltiVecPriyadarshan Kolte, Roger Smith, Su Wen. 384-391 [doi]
- Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning TreesGuo-Hui Lin, Guoliang Xue, Defang Zhou. 392 [doi]
- Design for Testability to Combat Delay FaultsJacob Savir. 407-411 [doi]
- Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-CircuitsIrith Pomeranz, Sudhakar M. Reddy. 412-417 [doi]
- Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-ChipAbhijit Jas, Nur A. Touba. 418 [doi]
- Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular ApplicationsLucian Codrescu, D. Scott Wills. 428-435 [doi]
- Load-Balancing Branch Target Cache and Prefetch BufferChi-Hung Chi, Jun-Li Yuan. 436-441 [doi]
- Dynamic Branch Decoupled ArchitectureAkhilesh Tyagi, Hon-Chi Ng, Prasant Mohapatra. 442 [doi]
- Improving Witness Search Using Orders on StatesRobert W. Sumners, Jayanta Bhadra, Jacob A. Abraham. 452-457 [doi]
- Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic SimulationPranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya. 458-466 [doi]
- Efficient Fixpoint Computation for Invariant CheckingKavita Ravi, Fabio Somenzi. 467 [doi]
- A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load ApplicationsMauro Olivieri, Alessandro Trifiletti, Alessandro De Gloria. 476-481 [doi]
- A Methodology for Rapid Prototyping of Analog SystemsSree Ganesan, Ranga Vemuri. 482-488 [doi]
- Transmission Line Clock DriverMatthew Becker, Thomas F. Knight Jr.. 489 [doi]
- Benchmarking, Selection and Debugging of MicrocontrollersAlan Weiss. 492-498 [doi]
- DSP for the Third Generation Wireless CommunicationsUming Ko, Mike McMahan, Edgar Auslander. 516-520 [doi]
- Performance and Reliability Verification of C6201/C6701 Digital Signal ProcessorsNagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor. 521 [doi]
- Pursuing the Performance Potential of Dynamic Cache Line SizesPeter van Vleet, Eric J. Anderson, Lindsay Brown, Jean-Loup Baer, Anna R. Karlin. 528-537 [doi]
- The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache EfficiencyBrian R. Fisk, R. Iris Bahar. 538-545 [doi]
- Cache Optimization for Memory-Resident Decision Support Commercial WorkloadsPedro Trancoso, Josep Torrellas. 546 [doi]
- An Investigation of Power Delay Tradeoffs for Dual Vt CMOS CircuitsQi Wang, Sarma B. K. Vrudhula. 556-562 [doi]
- Delay Optimization of CMOS Logic Circuits Using Closed-Form ExpressionsMaitham Shams, Mohamed I. Elmasry. 563-568 [doi]
- Design and Synthesis of Monotonic CircuitsTyler Thorp, Gin Yee, Carl Sechen. 569-572 [doi]
- SOI Implementation of a 64-Bit AdderJ. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak. 573 [doi]
- TriMedia CPU64 Application Domain and Benchmark SuiteA. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans. 580-585 [doi]
- TriMedia CPU64 ArchitectureJos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel. 586-592 [doi]
- TriMedia CPU64 Application Development EnvironmentEvert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndhoven, P. Struik, Pieter van der Wolf, Frans Sijstermans, M. J. A. Tromp, Jan-Willem van de Waerdt. 593-598 [doi]
- TriMedia CPU64 Design Space ExplorationGerben J. Hekstra, G. D. La Hei, Peter Bingley, Frans Sijstermans. 599 [doi]
- On State Assignment of Finite State Machines Using Hypercube Embedding ApproachImtiaz Ahmad, Raza Ul-Mustafa. 608-613 [doi]
- Synthesis of Arrays and RecordsPradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi. 614-619 [doi]
- Decomposition of Finite State Machines for Area, Delay MinimizationRupesh S. Shelar, Madhav P. Desai, H. Narayanan. 620-625 [doi]
- BDD Decomposition for Efficient Logic SynthesisCongguang Yang, Maciej J. Ciesielski, Vigyan Singhal. 626 [doi]
- Software Synthesis for Complex Reactive Embedded SystemsFelice Balarin, Massimiliano Chiodo. 634-639 [doi]
- Hardware/Software Partitioning of Multirate System Using Static Scheduling TheoryRomain Kamdem, Alain Fonkoua, Andre Zenatti. 640-645 [doi]
- Compositional Software Synthesis of Communicating ProcessesXiaohan Zhu, Bill Lin. 646-651 [doi]
- Preference-Driven Hierarchical Hardware/Software PartitioningGang Quan, Xiaobo Hu, Garrison W. Greenwood. 652 [doi]