Abstract is missing.
- N+1 subtractors for weighted operandsCostas Efstathiou. 1-4 [doi]
- An efficient dual-mode floating-point Multiply-Add Fused UnitKonstantinos Manolopoulos, Dionysios I. Reisis, Vassilios A. Chouliaras. 5-8 [doi]
- RNS multi-voltage low-power multiply-add unitIoannis Kouretas, Vassilis Paliouras. 9-12 [doi]
- Analysis of compressor architectures in MOS current-mode logicGiuseppe Caruso, Daniela Di Sclafani. 13-16 [doi]
- Alternatives for low-complexity complex rotatorsFahad Qureshi, Mario Garrido, Oscar Gustafsson. 17-20 [doi]
- A compact voltage-controlled transconductor with high linearityManuel Pedro, Juan Antonio Gómez Galán, Trinidad Sanchez-Rodriguez, R. Jimenez, Clara Isabel Lujan-Martinez, Ramón González Carvajal. 21-24 [doi]
- Fast-settling low-power two-stage self-biased CMOS amplifier using feedforward-regulated cascode devicesEdinei Santin, Michael Figueiredo, Rui Tavares, João Goes, Luís B. Oliveira. 25-28 [doi]
- A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-NM CMOSSyed Ahmed Aamir, J. Jacob Wikner. 29-32 [doi]
- 16-channel readout ASIC for a hodoscopeShi-ming Deng, Herve Mathez, Denis Dauvergne, Guo-Neng Lu. 33-36 [doi]
- Sizing analog circuits using an SQP and Branch and Bound based approachMichael Pehl, Michael Zwerger, Helmut E. Graeb. 37-40 [doi]
- First Order Noise Shaping Local-Oscillator Based Time-to-Digital ConverterFrancesco Brandonisio, Michael Peter Kennedy, Franco Maloberti. 41-44 [doi]
- Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuitAntonio J. Ginés, Ricardo Doldán, Adoración Rueda, Eduardo J. Peralías. 45-48 [doi]
- Frequency down-conversion with complementary-MOS invertersHervé Barthélemy, Edith Kussener, Sylvain Bourdel, Wenceslas Rahajandraibe. 49-52 [doi]
- A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS processChiou-Bang Chen, Horng-Yuan Shih. 53-56 [doi]
- From nanoscale technology scenarios to compact device models for ambipolar devicesSébastien Fregonese, Cristell Maneux, Thomas Zimmer. 57-61 [doi]
- Emerging memory technologies for reconfigurable routing in FPGA architecturePierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Giovanni Betti Beneventi, Fabien Clermidy, Luca Perniola. 62-65 [doi]
- Logic cells and interconnect strategies for nanoscale reconfigurable computing fabricsIan O'Connor, Kotb Jabeur, David Navarro, Nataliya Yakymets, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy. 66-69 [doi]
- Synthesis of regular computational fabrics with ambipolar CNTFET technologyMichele De Marchi, Shashikanth Bobba, M. Haykel Ben Jamaa, Giovanni De Micheli. 70-73 [doi]
- Reconfigurable Ultra Low Power LNA for 2.4GHz Wireless Sensor NetworksThierry Taris, Aya Mabrouki, Hassene Kraimia, Yann Deval, Jean-Baptiste Begueret. 74-77 [doi]
- Reconfigurable multiband multimode LNA for LTE/GSM, WiMAX, and IEEE 802.11.a/b/g/nAnh-Tuan Phan, Ronan Farrell. 78-81 [doi]
- CMOS LNA optimization techniques: Comparative studyVasilis Papageorgiou, Spyros Vlassis. 82-85 [doi]
- A Variable Gain Multiband Shunt Feedback LNA for LTEStefan Kaehlert, Dirk Bormann, Ralf Wunderlich, Stefan Heinen. 86-89 [doi]
- Optimized passive devices for low-power LNA designIgnacio Gil, Raúl Fernández, Javier J. Sieiro, José María López-Villegas. 90-93 [doi]
- A linear digital VCO for Clock Data Recovery (CDR) applicationsRyan Helinski, Thomas LeBoeuf, Colby Hoffman, Payman Zarkesh-Ha. 98-101 [doi]
- Process-variation tolerant design techniques for multiphase clock generationManohar Nagaraju, Wei Wu, Cameron T. Charles. 102-105 [doi]
- A 3 GHz DLL-based clock generator with stuck locking protectionYo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng. 106-109 [doi]
- Design of a 7-bit 1GSPS folding-interpolation A/D converter with self-calibration techniqueYounghoon Kim, Jungwon Jeon, Kyuik Cho, Daeyun Kim, Joonho Moon, Minkyu Song. 110-113 [doi]
- Calibration of high-resolution flash ADCS based on histogram test methodsArmin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner, Kent Palmkvist, Mark Vesterbacka. 114-117 [doi]
- Pseudorandom sequence generation for mismatch analog compensation of ADCsVictor R. Gonzalez-Diaz, Edoardo Bonizzoni, Franco Maloberti. 118-121 [doi]
- A low-power 12-bit 2nd-order Σ-Δ analog-to-digital converter for CMOS image sensorsGun-Hee Yun, Min-Kyu Kim, Jong-Boo Kim, Min-Seok Shin, Oh-Kyong Kwon. 122-125 [doi]
- A cluster-head selection algorithm for Wireless Sensor NetworksAshish Rajshekhar Chalak, Sudip Misra, Mohammad S. Obaidat. 130-133 [doi]
- An efficient procedure for packet collision resolution in wireless slotted ALOHA MIMO systemsNejah Missaoui, Inès Kammoun, Mohamed Siala. 134-137 [doi]
- Workcell concatenation using wifi-based Wireless Networked Control SystemsTarek K. Refaat, Ramez M. Daoud, Hassanein H. Amer, Mai M. Hassan, Omneya M. Sultan. 138-141 [doi]
- A mechanism for reducing congestion while routing bulky data in Mobile Ad Hoc NetworksSanjay Kumar Dhurandher, Mohammad S. Obaidat, Khushboo Diwakar. 142-145 [doi]
- Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switchJorge Tonfat, Ricardo Reis. 146-149 [doi]
- Random forests-based 2D-to-3D video conversionMahsa T. Pourazad, Panos Nasiopoulos, Ali Bashashati. 150-153 [doi]
- Direct approach to image edge detection using differentiatorsMohamad Adnan Al-Alaoui. 154-157 [doi]
- Error measures for segmentation results: Evaluation on synthetic imagesAicha-Baya Goumeidane, Mohammed Khamadja. 158-161 [doi]
- Guidelines for capturing high quality stereoscopic content based on a systematic subjective evaluationDi Xu, Lino Coria-Mendoza, Panos Nasiopoulos. 162-165 [doi]
- Calibration of input-match and its center frequency for an inductively degenerated low noise amplifierSami Mahersi, Hassène Mnif, Mourad Loulou. 166-169 [doi]
- Sub-THz high gain wide-band low noise amplifiers in 90nm RF CMOS technologyAmneh Akour, Waleed Khalil, Mohammed Ismail. 174-177 [doi]
- Inductive coupling for imbalance improvement in a UWB balun employed in a folded cascode mixerDimitrios Mavridis, Michail Papamichail, Grigorios Kalivas, George D. Papadopoulos. 178-181 [doi]
- A 109dB PSRR, 31µW fully-MOSFET bandgap voltage reference in 0.13µm CMOS technologyKianoush Souri, Hossein Shamsi, Sarvenaz Samadian, Hossein Mirzaie. 182-185 [doi]
- Low-area tunable CMOS resistor with improved linearityCasmin Popa. 190-193 [doi]
- Electronically tunable PLL controller design using OTABhaba Priyo Das, Neville Watson, Yonghe Liu. 198-202 [doi]
- Technique of 3D NILT based on complex Fourier series and quotient-difference algorithmLubomír Brancík. 203-206 [doi]
- Low-voltage rail-to-rail bulk-driven CMFB network with improved gain and bandwidthFernando Castaño, Guido Torelli, Raquel Pérez-Aloe, Juan M. Carrillo. 207-210 [doi]
- Reconfigurable pseudo floating-gate analog circuitsYngvar Berg, Mehdi Azadmehr. 211-214 [doi]
- Digitally-controlled DC-DC converter with variable switching frequencyRobert Priewasser, Matteo Agostinelli, Stefano Marsili, Mario Huemer. 219-222 [doi]
- 433 MHz implantable wireless stimulation of spinal nervesJoão Paulo Carmo, José Carlos Ribeiro, Joao F. Ribeiro, Manuel F. Silva, Paulo Mateus Mendes, José Higino Correia. 223-226 [doi]
- A complete device dedicated to ECG signal measurement with integrated 3D Hall sensor for signal correctionNicolas Pillet, Mohsen Ayachi, Vincent Frick, Hervé Berviller, Jacques Felblinger, Jean-Philippe Blonde. 227-230 [doi]
- Progress in self-stabilizing capsules for imaging of the large intestineDobromir Filip, Orly Yadid-Pecht, Martin P. Mintchev. 231-234 [doi]
- SoC architecture for real-time interactive painting based on lattice-BoltzmannDomien Nowicki, Luc Claesen. 235-238 [doi]
- A digital IC Random Number Generator with logic gates onlyÜlkühan Güler, Salih Ergün, Günhan Dündar. 239-242 [doi]
- Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processorHarris E. Michail, George Athanasiou, George Makridakis, Costas E. Goutis. 243-246 [doi]
- Control Unit for a Continuous Variable Transmission for use in an Electric CarFrancarl Galea, Edward Gatt, Owen Casha, Ivan Grech. 247-250 [doi]
- A flexible realtime system for broadband time-frequency analysis in 130 NM CMOSLudovic Noury, Habib Mehrez. 251-254 [doi]
- A FPGA implementation of low-complexity noise removalTakeaki Matsubara, Vasily G. Moshnyaga, Koji Hashimoto. 255-258 [doi]
- A NoC-based multi-{soft}core with 16 coresEduard Fernandez-Alonso, David Castells-Rufas, Sergi Risueño, Jordi Carrabina, Jaume Joven. 259-262 [doi]
- Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimationJosep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche. 263-267 [doi]
- ASPEN: An Asynchronous Signal Processor for Energy Efficient Sensor NodesSoumik Ghosh, Jared Tessier, Magdy A. Bayoumi. 268-272 [doi]
- Optimal modulus sets for efficient residue-to-binary conversion using the New Chinese Remainder TheoremsNarendran Narayanaswamy, Alexander Skavantzos, Thanos Stouraitis. 273-276 [doi]
- A dynamic DFI-compatible strobe qualification system for Double Data Rate (DDR) physical interfacesAlexis Alexandropoulos, Fotis Plessas, Michael K. Birbas. 277-280 [doi]
- Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scalingHamid Reza Pourshaghaghi, José Pineda de Gyvez. 281-284 [doi]
- Novel wide voltage range level shifter for near-threshold designsMaryam Ashouei, Herman Luijmes, Jan Stuijt, Jos Huisken. 285-288 [doi]
- Gate oxide trap characterization under DC and pulse stressSangku Park, Jaehoon Lee, Y. Ryu, J. Kang, B. So, Dohyun Baek. 289-292 [doi]
- Novel high speed and ultra low voltage CMOS flip-flopsYngvar Berg. 293-296 [doi]
- VB-DVFS: A new algorithm for power efficiency of CMP with GALSDuan Wei, Fan Qi Fei, Huang Kun, Zhang Ge. 297-300 [doi]
- Characteristics of double-gate polycrystalline silicon thin-film transistors for AMOLED pixel designIlias Pappas, Dimitrios H. Tassis, Stilianos Siskos, Charalambos A. Dimitriadis. 301-304 [doi]
- A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nmArash Abadian, Mojtaba Lotfizad, Nasser Erfani Majd, Mohammad Bagher Ghaznavi Ghoushchi, H. Mirzaie. 305-310 [doi]
- X-axis spatial redundancy supression: Contribution to the integration of smart reading techniques in a standard CMOS vision sensorHawraa Amhaz, Gilles Sicard. 311-314 [doi]
- Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuitMohammed Bougataya, Oussama Berriah, Ahmed Lakhssassi, Adel Omar Dahmane, Yves Blaquière, Yvon Savaria, Richard Norman, Richard Prytula. 315-318 [doi]
- Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approachHans Kristian Otnes Berge, Matthias W. Blesken, Snorre Aunet, Ulrich Rückert. 319-322 [doi]
- Towards an IEEE 802.15.4 SDR transceiverJosep Sabater, Jose Maria Gómez, Manel Lopez. 323-326 [doi]
- Verification of a VHDL GPS baseband processor using a simulink-based test bench generatorTerence Zarb, Ivan Grech, Edward Gatt, Owen Casha, Joseph Micallef. 327-330 [doi]
- Performance analysis of the MAP turbo-equalizer and mapping optimization for BICMSihem Châabouni, Noura Sellami, Mohamed Siala. 331-334 [doi]
- A modified Rijndael algorithm and it's implementation using FPGAAhmed A. Mohamed, Ahmed H. Madian. 335-338 [doi]
- Source compensation scheme for reducing impact of variability on differential amplifier in 35nm CMOSFeng Hong, David R. S. Cumming. 339-342 [doi]
- A behavioral and temperature measurements-based modeling of an operational amplifier using VHDL-AMSSahbi Baccar, Timothée Levi, Dominique Dallet, Vladimir Shitikov, François Barbara. 343-346 [doi]
- 0.8V bulk-driven variable gain amplifierGeorge Raikos, Spiridon Vlassis. 347-350 [doi]
- A low-voltage current sorting circuit based on 4-T min-max CMOS switchJordi Madrenas, Daniel Fernández, Jordi Cosp. 351-354 [doi]
- A versatile technique for linearly tunable transconductorsGeorge Raikos, Spiridon Vlassis. 355-358 [doi]
- Data detection for cooperative vehicular communication systems with unknown channelsLanlan He, Shaodan Ma, Yik-Chung Wu, Tung-Sang Ng. 359-362 [doi]
- Resource allocation algorithm for MIMO-OFDMA systems with minimum resources guaranteeVasileios D. Papoutsis, Ioannis G. Fraimis, Stavros A. Kotsopoulos. 363-366 [doi]
- A reactive Optimized Link State Routing protocol for Mobile ad hoc networksSanjay Kumar Dhurandher, Mohammad S. Obaidat, Mukta Gupta. 367-370 [doi]
- Adaptive power reconfigurability for preventing excessive power dissipation in wireless receiversAlp Oguz, Dominique Morche, Catherine Dehollain, Erkan Nevzat Isa. 371-374 [doi]
- Tracking-optimal pre- and post-processing for H.264 compression in traffic video surveillance applicationsEren Soyak, Sotirios A. Tsaftaris, Aggelos K. Katsaggelos. 375-378 [doi]
- Hardware implementation of fast forwarding engine using standard memory and dedicated circuitKazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka. 379-382 [doi]
- High performance architectures for the arithmetic encoder of the H.264/AVC CABAC entropy coderVagner S. Rosa, Leandro Max Silva, Sergio Bampi. 383-386 [doi]
- A high throughput pipelined architecture for H.264/AVC deblocking filterNikolaos Kefalas, George Theodoridis. 387-391 [doi]
- A low-cost hardware architecture binarizer design for the H.264/AVC CABAC entropy codingAndré Luís Del Mestre Martins, Vagner S. Rosa, Sergio Bampi. 392-395 [doi]
- A 2.9-30.3GHz fourth-harmonic voltage-controlled oscillator in 130nm SiGe BiCMOS technologyYang Lin, David E. Kotecki. 396-399 [doi]
- A low power low phase noise CMOS voltage-controlled oscillatorMohammad Niaboli-Guilani, Alireza Saberkari, Reza Meshkin. 422-425 [doi]
- A 0.8-13.4GHz combined voltage-controlled oscillator with an exclusive-OR in 130nm SiGe BiCMOSYang Lin, David E. Kotecki. 426-429 [doi]
- Physical design tradeoffs in power distribution networks for 3-D ICsIoannis Tsioutsios, Vasilis F. Pavlidis, Giovanni De Micheli. 430-433 [doi]
- Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operationsJiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens, Peter Gillen. 434-437 [doi]
- Transient current and delay analysis for resistive-open defects in future 16 nm CMOS circuitsMohammad Fawaz, Nader Kobrosli, Ahmad Chkeir, Ali Chehab, Ayman I. Kayssi. 438-441 [doi]
- Yield enhancement by tube redundancy in CNFET-based circuitsRehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra. 442-445 [doi]
- A new architecture of companding integrator for CMOS current-mode analog filtersLucas C. D'Eça, Robson Nunes de Lima, Ana Isabela Araújo Cunha. 446-449 [doi]
- Improved linearity CMOS active resistor based on complementary computational circuitsCosmin Popa. 450-453 [doi]
- Design of low-voltage log-domain filters with maximized dynamic rangeVasilis Kolios, Costas Psychalinos. 454-457 [doi]
- Differential voltage class-AB current controlled current conveyorFilomila Kafe, Costas Psychalinos. 458-461 [doi]
- A low-pass filter with automatic frequency tuning for a bluetooth receiverManuel Pedro, Juan Antonio Gómez Galán, Trinidad Sanchez-Rodriguez, Fernando Muñoz Chavero, Ramón González Carvajal, Antonio J. López-Martín. 462-465 [doi]
- Design of parallel LDPC interleaver architecture: A bipartite edge coloring approachAwais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin 0001. 466-469 [doi]
- VLSI implementation and performance of turbo decoding stopping criteriaAngelos Spanos, Vassilis Paliouras. 470-474 [doi]
- TDTL architecture with fast error correction techniqueOmar Al-Kharji Al-Ali, Nader Anani, Prasad V. S. Ponnapalli, Mahmoud Al-Qutayri, Saleh R. Al-Araji. 475-478 [doi]
- Calculation of cycle lengths in higher-order MASH DDSMs with constant inputsBrian Fitzgibbon, Michael Peter Kennedy. 479-482 [doi]
- Extension of the DSL coverage area for High Definition IPTV VOD services using H.264 Scalable Video CodingAnne-Sophie Bacquet, Christophe Deknudt, Patrick Corlay, Mohamed Gharbi, François-Xavier Coudoux. 483-486 [doi]
- MPEG-4 AVC stream watermarking by ST-mDM techniquesMarwen Hasnaoui, Maher Belhaj, Mihai Mitrea, Françoise J. Prêteux. 487-490 [doi]
- Low complexity H.264/AVC spatial resolution transcoding in the transform domainAnne-Sophie Bacquet, Christophe Deknudt, Patrick Corlay, François-Xavier Coudoux, Marc Gazalet. 491-494 [doi]
- An on-chip parallel memory architecture for a stereo vision systemAndy Motten, Luc Claesen. 495-498 [doi]
- Real-time canny edge detection parallel implementation for FPGAsChristos Gentsos, Calliope-Louisa Sotiropoulou, Spiridon Nikolaidis, Nikolaos Vassiliadis. 499-502 [doi]
- A compact model for MM-wave transmission lines and interconnects on lossy CMOS substratesAmneh Akour, Waleed Khalil, John L. Volakis, Mohammed Ismail. 503-506 [doi]
- Novel designs for high-efficiency millimeter-wave zero-bias detectorsChun-Yen Huang, Chin-Chung Nien, Chen-Ming Li, Ya-Chung Yu, Li-Yuan Chang, Jenn-Hwan Tarng. 507-510 [doi]
- Low power millimeter wave active sige sub-harmonic up-conversion mixer with ultra low driving powerKok Meng Lim, Jiangmin Gu, Yang Lu, Jinna Yan, Wei Meng Lim, Kaixue Ma, Kiat Seng Yeo. 511-514 [doi]
- Improved design of the BB-SoC which incorporated the ultra high speed multi level QAM modem for MM-wave radio systems, and its performanceKazuya Kojima, Yasuhiro Toriyama, Masatoshi Nagayasu, Toru Taniguchi. 515-518 [doi]
- Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designsAshoka Visweswara Sathanur, Jos Huisken, Jan Stuyt, Harmke de Groot. 519-522 [doi]
- Resource-aware task allocation and scheduling for segbus platformKhalid Latif 0002, Tiberiu Seceleanu, Cristina Cerschi Seceleanu, Hannu Tenhunen. 523-526 [doi]
- NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGASHarry Sidiropoulos, Kostas Siozios, Dimitrios Soudris. 527-530 [doi]
- Bitwidth-aware high-level synthesis for designing low-power DSP applicationsGhizlane Lhairech-Lebreton, Philippe Coussy, Dominique Heller, Eric Martin 0001. 531-534 [doi]
- BIT-width exploration over 3D architectures using high-level synthesisIoannis Koutras, Antonis Papanikolaou, George Economakos, Dimitrios Soudris. 535-538 [doi]
- Optimal filtering of incremental first-order sigma-delta modulators with sweep inputSylvain Maréchal, François Krummenacher, Maher Kayal. 539-542 [doi]
- Time-domain equivalent design of continuous-time ΣΔ modulatorsOscar Belotti, Franco Maloberti. 543-546 [doi]
- A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulatorsYang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. 547-550 [doi]
- A low-power delta-sigma modulator using dynamic-source-follower integratorsRyoto Yaguchi, Fumiyuki Adachi, Takao Waho. 551-554 [doi]
- A 0.5V 94dB SNR CT-ΣΔ modulator for implantable and portable biomedical devicesAlfredo Farid Bautista, Sergio Omar Martinez-Chapa, Olivier Rossetto, Graciano Dieck-Assad. 555-558 [doi]
- The low-cost implement of a phase coding SSVEP-Based BCI systemKuo-Kai Shyu, Po-Lei Lee, Ming-Huan Lee, Yun-Jen Chiu. 559-562 [doi]
- Scalable low cost architecture for analysis of Lab-on-Chip dataSpyridon Blionas. 563-566 [doi]
- A full digital low power dpsk demodulator and clock recovery circuit for high data rate neural implantsAymen Ghenim, Mohamed Ghorbel, Ahmed Ben Hamida. 571-574 [doi]
- Memory-aware multiple reference frame motion estimation for the H.264/AVC standardMateus Grellert, Felipe Sampaio, Bruno Hecktheuer, Júlio C. B. de Mattos, Luciano Volcan Agostini. 575-578 [doi]
- Shape independent VLSI-architecture design approach for 2D morphological operations with non-flat structuring elementsMarkus Holzer, Frank Schumacher, Thomas Greiner, Wolfgang Rosenstiel. 579-582 [doi]
- Efficient hardware solution for low power and adaptive image-compression in WSNMed Lassaad Kaddachi, Adel Soudani, Ibtihel Nouira, Vincent Lecuire, Kholdoun Torki. 583-586 [doi]
- A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC encondingFábio Luís Livi Ramos, Bruno Zatt, Thaísa Leal da Silva, Altamiro Amadeu Susin, Sergio Bampi. 587-590 [doi]
- Homogeneity and distortion-based intra mode decision architecture for H.264/AVCGuilherme Corrêa, Cláudio Machado Diniz, Sergio Bampi, Daniel Palomino, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini. 591-594 [doi]
- A 65nm CMOS fully integrated 31.5 dBm triple SFDS Power Amplifier dedicated to W-CDMA applicationYohann Luque, Nathalie Deltimple, Eric Kerherve, Didier Belot. 595-598 [doi]
- A novel 2.4 GHz CMOS class-E power amplifier with efficient power control for wireless communicationsReza Meshkin, Alireza Saberkari, Mohammad Niaboli-Guilani. 599-602 [doi]
- A fully differential monolithic 2.4GHZ PA for IEEE 802.15.4 based on efficiency design flowRafaella Fiorelli, Eduardo J. Peralías, Nicolás Barabino, Fernando Silveira. 603-606 [doi]
- Comparative efficiency analysis of dynamically supplied power amplifiers (PA)Orlando Lazaro, Gabriel A. Rincón-Mora. 607-610 [doi]
- Design of energy efficient power amplifier for 4G user terminalsAbubakar Sadiq Hussaini, Raed A. Abd-Alhameed, Jonathan Rodriguez. 611-614 [doi]
- Short-circuit energy dissipation model for sub-100nm CMOS buffersLabros Bisdounis. 615-618 [doi]
- Optimal specification of a receiver blocks from global specifications: Example of IEEE 802.15.4Papy Ndungidi, Ursula Dongmo, Fortunato Dualibe, Carlos Valderrama. 619-622 [doi]
- Estimating design quality of digital systems via machine learningQi Guo, Tianshi Chen, Haihua Shen, Yunji Chen. 623-626 [doi]
- Genetic algorithm based variable ordering of BDDs for multi-level logic optimization with area-power trade-offsSaurabh Chaudhury, Anirban Dutta. 627-630 [doi]
- Synthesis of provably-correct hardware with optionsMichael F. Dossis. 631-634 [doi]
- New approach for enhancing efficiency of computer aided design in circuit simulationDavid Cerny, Josef Dobes. 635-638 [doi]
- Latency and power optimization in AAA methodology for integrated circuitsYaroub Elloumi, Mohamed Akil, Thierry Grandpierre, Mohamed Bedoui Hedi. 639-642 [doi]
- Routing algorithms performance in different routing scopesTiago Reimann, Glauco B. V. Santos, Ricardo A. L. Reis. 643-646 [doi]
- Lattice-basedmemory allocation for data-intensive signal processing applicationsDoru V. Nasui, Florin Balasa. 647-650 [doi]
- A study on layout quality of automatic generated cellsGracieli Posser, Adriel Ziesemer, Daniel Guimares Jr., Gustavo Wilke, Ricardo A. L. Reis. 651-654 [doi]
- Simulation-based optimization of CCIIs' performances in weak inversionAmin Sallem, Ivick Guerra-Gómez, Mourad Fakhfakh, Mourad Loulou, Esteban Tlelo-Cuautle. 655-658 [doi]
- Timing verification of cyclic systems based on temporal constraint analysisAhmed Azzabi, El Mostapha Aboulhamid, Gabriela Nicolescu. 659-662 [doi]
- Design and implementation of a soft-decision decoder for Cortex codesPatrick Adde, Christophe Jégo, Raphaël Le Bidan, Jorge Ernesto Pérez Chamorro. 663-666 [doi]
- A low-noise wide range delta-sigma frequency synthesizer for DTV broadbandTe-Wen Liao, Jun-Ren Su, Chung-Chih Hung. 667-670 [doi]
- A 3.2Gbps single-ended receiver using self-reference generation technique for DRAM interfaceHyeon-Cheon Seol, Jun-Yong Song, Kang-Sub Kwak, Oh-Kyong Kwon. 671-674 [doi]
- Interferer performance dependency on analog-digital-conversion of GNSS-class signals in GPS receiversChristoph Schultz, Markus Hammes, Rainer Kreienkamp, Lars Lemke, Stefan van Waasen. 675-678 [doi]
- The frequency spectrum of polar modulated PWM signals and the image problemShuli Chi, Christian Vogel, Peter Singerl. 679-682 [doi]
- A two op-amps third-order ΣΔ modulator with complex conjugate NTF zerosAldo Pena-Perez, Oscar Belotti, Edoardo Bonizzoni, Franco Maloberti. 683-686 [doi]
- Direct residue-to-analog conversion scheme based on Chinese Remainder TheoremOmar Abdelfattah, Andraws Swidan, Zeljko Zilic. 687-690 [doi]
- Modeling micromelodic effects in standard Arabic using MOMELAmina Chentir, Daniel J. Hirst, Mhania Guerti. 691-693 [doi]
- A new method for enhancement of the noisy speech with low SNRRoghayeh Doost, Abolghasem Sayadiyan, Hossein Shamsi, Hossein Mirzaie. 698-701 [doi]
- Automatic segmentation of brain tumors from MR images using undecimated wavelet transform and gabor waveletsGayatri Mirajkar, Balaji Barbadekar. 702-705 [doi]
- Stream implementation of serial morphological filters with approximated polygonsJan Bartovsky, Petr Dokládal, Eva Dokladalova, Vjaceslav Georgiev. 706-709 [doi]
- VHDL implemetation of a DMX512 decoder on a FPGANicholas Attard, Steve Camilleri, Roberto Drago, Maverick Hili, Owen Casha, Edward Gatt, Ivan Grech. 710-713 [doi]
- A low-area filter bank design methodology for on-chip ADC testingNicolas Mechouk, Dominique Dallet, Lilian Bossuet, Bertrand Le Gal. 718-721 [doi]
- Estimating complexity in multi rate systemsThomas Schlechter. 726-729 [doi]
- A continuous-flow, Variable-Length FFT SDF architectureNikolaos Polychronakis, Dionysios I. Reisis, Emmanouil Tsilis. 730-733 [doi]
- 2 fast Fourier transform algorithmMonir Taha Hamood, Said Boussakta. 734-737 [doi]
- A high performance full pipelined arquitecture of MLP Neural Networks in FPGAAntonyus P. Do A. Ferreira, Edna Natividade da Silva Barros. 742-745 [doi]
- Model-based design flow for NoC-based MPSoCsLuciano Ost, Leandro Soares Indrusiak, Sanna Määttä, Marcelo Mandelli, Jari Nurmi, Fernando Moraes. 750-753 [doi]
- Improved MPSoC co-design methodology for stream oriented processing applicationsAbdelHalim Samahi, Mounir Boukadoum. 754-757 [doi]
- Power- and performance-aware IP mapping for NoC-based MPSoC platformsKhalid Latif 0002, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen. 758-761 [doi]
- SysPy: using Python for processor-centric SoC designEvangelos Logaras, Elias S. Manolakos. 762-765 [doi]
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- A fully integrated 4GHz continuous-time bandpass Delta-Sigma converterQuentin Beraud-Sudreau, Andre A. Mariano, Dominique Dallet, Yann Deval, Jean-Baptiste Begueret. 778-781 [doi]
- ® for advanced RF receiver architecturesFrancesco Cannone, Gianfranco Avitabile, Giuseppe Coviello, Damiano Cascella. 782-785 [doi]
- All-digital TAD-OFDM detection for sensor interface using TAD-digital synchronous detectionTakamoto Watanabe, Tomohito Terasawa. 786-789 [doi]
- SDR waveform components implementation on single FPGA multiprocessor platformMuhammad Imran Taj, Omar Hammami, M. Akil. 790-793 [doi]
- Study of broadband postbeamformer interference canceler antenna array processor using orthogonal interference beamformerLal C. Godara, Presila Israt. 794-797 [doi]
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- A low-cost current sensor with a novel modulated interface (F-PWM)Abdoulkarim Bouabana, Constantinos Sourkounis. 802-806 [doi]
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- Direct design of bandstop wave digital lattice filtersMohamed Yaseen. 847-850 [doi]
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- Wide-band receiver architecture with flexible blocker filtering techniquesChristian Izquierdo, Andreas Kaiser, Franck Montaudon, Philippe Cathelin. 894-897 [doi]
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- Organic memristive device and its application for the information processingVictor Erokhin, Marco P. Fontana. 926-929 [doi]
- Memristive systems analysis of 3-terminal devicesBlaise Mouttet. 930-933 [doi]
- A review on memristive devices and applicationsThemistoklis Prodromakis, Chris Toumazou. 934-937 [doi]
- Cellular neural networks with memristive cell devicesGyörgy Cserey, Ádám Rák, Balázs Jakli, Themistoklis Prodromakis. 938-941 [doi]
- A front end chip development for the SLHC CMS Slicon Strip TrackerHervé Chanal, Didier Contardo, Yannick Zoccarato. 942-945 [doi]
- Digital cochlea model implementation using Xilinx XC3S500E Spartan-3E FPGAIsabel Gambin, Ivan Grech, Owen Casha, Edward Gatt, Joseph Micallef. 946-949 [doi]
- Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughputStephan Hartmann, Stefan Schiefer, Stefan Scholze, Johannes Partzsch, Christian Mayr, Stephan Henker, René Schüffny. 950-953 [doi]
- Design of a low latency spectrum analyzer using the Goertzel Algorithm with a Network on ChipLaurent Jojczyk, Paulo Da Cunha Possa, Carlos Valderrama. 954-957 [doi]
- Traceability from "farm to fork" using RFID technologyPhilippos Tragas, Elias S. Manolakos. 958-961 [doi]
- A GA-based method for efficient interconnect capacitance computation in mixed-signal integrated circuits using sets of linear chargesYiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos. 962-965 [doi]
- Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrateRemi Pulicani, Olivier Goducheau, Hubert Degoirat, Hassen Aziza, Annie Pérez, Emmanuel Bergeret. 966-969 [doi]
- A statistical design method for Giga Bit memory arrays and beyondChristian Caillat, Eric Carman, Jean Michel Daga, Cedric Ouvrard, Philippe Bauser. 970-973 [doi]
- Low leakage multi-Vth technique for sequential circuits at transistor level in nanotechnologyAbdoul Rjoub, Hassan Almanasrah. 974-977 [doi]
- A true zero-load stable CMOS capacitor-free low-dropout regulator with excessive gain reductionJohn Hu, Mohammed Ismail. 978-981 [doi]
- A digitally controlled linear voltage regulator in a 65nm CMOS processThomas Jackum, Gerhard Maderbacher, Wolfgang Pribyl, Roman Riederer. 982-985 [doi]
- State-dependent ADC scheme for digitally isolated SMPCMartin Scharrer, Mark Halton, Tony Scanlan, Karl Rinne. 986-989 [doi]
- Effective modeling of temperature effects on lithium polymer cellsFederico Baronti, Gabriele Fantechi, Emanuele Leonardi, Roberto Roncella, Roberto Saletti. 990-993 [doi]
- Nonlinear robust control for DC-DC convertersArgiris G. Soldatos, Petros P. Karamanakos, Konstantinos G. Pavlou, Stefanos N. Manias. 994-997 [doi]
- Control for high-speed archimedean spiral nanopositioningAndreas Kotsopoulos, Aggeliki Pantazi, Theodore Antonakopoulos. 998-1001 [doi]
- Parameter Dependent Lyapunov functions for stability of Linear Parameter Varying systemsNedia Aouani, Salah Salhi, Germain Garcia, Mekki Ksouri. 1002-1005 [doi]
- Chaos control in a transmission line modelIoana Triandaf. 1006-1008 [doi]
- Fundamental reliability issues of advanced charge-trapping Flash memory devicesLuca Larcher, Andrea Padovani. 1009-1012 [doi]
- Phase-change RAM modelling and design via a Gillespie-type cellular automata approachJorge Vazquez, Peter Ashwin, Krisztian I. Kohary, C. David Wright. 1013-1016 [doi]
- Multilevel phase-change memoryNikolaos Papandreou, Aggeliki Pantazi, Abu Sebastian, Matthew J. Breitwisch, Chung Hon Lam, Haralampos Pozidis, Evangelos Eleftheriou. 1017-1020 [doi]
- Using flash memories as SIMO channels for extending the lifetime of solid-state drivesMaria Varsamou, Theodore Antonakopoulos. 1021-1024 [doi]
- Asynchronous CLS for Zero Crossing based CircuitsHariprasath Venkatram, Benjamin P. Hershberg, Un-Ku Moon. 1025-1028 [doi]
- Implementation of multi-channel LED driver with low inter-channel current deviation using self-optimized active current regulatorJae-Hyoun Park, Hyung-Do Yoon, Kyeung-Hak Seo. 1033-1036 [doi]
- Monolithic implementation of a double-scroll chaotic attractor and application to random number generationÜlkühan Güler, Salih Ergün. 1037-1040 [doi]
- Efficient testing of an optical feedback pixel driver using wavelet analysisMichael G. Dimopoulos, Alexios Spyronasios, Nikolaos P. Papadopoulos, Alkis A. Hatzopoulos. 1041-1044 [doi]
- An integrated voltage-mode PWM controlled buck converter with active compensationLei Liao, Tobias D. Werth, Stefan Kaehlert, Ralf Wunderlich, Stefan Heinen. 1045-1048 [doi]
- Design of 4-bit parallel sub-sampling A/D converter for IR-UWB receiverShenjie Wang, Zhiliang Hong. 1049-1052 [doi]
- Designing wideband voltage controlled oscillators for Software-Defined RadioMehul R. Naik, C. H. Vithalani. 1053-1056 [doi]
- A non-linear model for micropower rectifiers in UHF-band RFIDsXiao Liu, Catherine Dehollain. 1057-1060 [doi]
- Reflectometer Apparatus for rapid determination of water-cement ratioNazar T. Ali, Khalid Mubarak, Neil J. McEwan, Kahtan A. Mezher, Ahmed Kulaib, Adel Al-Zarouni. 1061-1063 [doi]
- A 2.3-GHz to 5.8-GHz CMOS receiver front-end for WiMAX/WLANSaul Rodriguez Duenas, Jad G. Atallah, Ana Rusu, Mohammed Ismail. 1068-1071 [doi]
- Analysis of parasitic effects of small-outline packages for high-frequency integrated circuitsChen Zhai, Muhammad Dawood. 1072-1075 [doi]
- A random-based fractional-N frequency divider for spurious tones cancellationNicolas Regimbal, Yann Deval, Franck Badets, Jean-Baptiste Begueret. 1076-1079 [doi]
- Low-complex BPSK demodulation using absolute comparisonYoungjoo Lee, Goeun Lim, In-Cheol Park. 1080-1083 [doi]
- Design of a double balanced square law CMOS up-conversion mixer with improved input isolation technique for high frequency applicationsS. M. Shahriar Rashid, A. B. M. H. Rashid. 1088-1091 [doi]
- Improved RF CMOS active inductor with high self resonant frequencyCristian Andriesei, Liviu Goras, Farid Temcamani, Bruno Delacressonniere. 1092-1095 [doi]
- Small signal characterization and modeling of LC-tanks fabricated in BiCMOS processCristian Andrei, Gregory Bassement, Didier Depreeuw, Guy Imbert. 1096-1099 [doi]
- Frequency scan technique for inkjet-printed chipless sensor Tag readingVíctor Montilla, Eloi Ramon, Jordi Carrabina. 1100-1103 [doi]
- Control of a robotic manipulator using neural network based predictive controlKamel Kara, Tedj Eddine Missoum, Kamel Eddine Hemsas, Mohamed Laid Hadjili. 1104-1107 [doi]
- Firmware/software platform for rapid development of PC-based data acquisition systemsFederico Baronti, Andrea Lazzeri, Roberto Roncella, Roberto Saletti. 1108-1111 [doi]
- Design, validation and FPGA implementation of a brushless DC motor speed controllerBogdan Alecsa, Alexandru Onea. 1112-1115 [doi]
- Frequency analysis of linear time-varying systemsShervin Erfani, Nima Bayan. 1116-1119 [doi]
- Online estimation of induction motor state space system using Recursive Least-SquaresBjarte Hoff, Waldemar Sulkowski. 1120-1123 [doi]
- A novel 1V, 24µW, ΣΔ modulator using Amplifier & Comparator Based Switched Capacitor technique, with 10-kHz bandwidth and 64dB SNDRShafqat Ali, Steve Tanner, Pierre-André Farine. 1124-1127 [doi]
- A low-voltage low-power Frequency-to-voltage converter for VCO feedback linearizationJørgen Andreas Michaelsen, Dag T. Wisland. 1132-1135 [doi]
- Built-in self calibration for process variation in single-loop continuous-time sigma-delta modulatorsJulian Garcia, Ana Rusu. 1136-1139 [doi]
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