Abstract is missing.
- Connecting E-Dreams to Deep-Submicron RealitiesHugo De Man. 1 [doi]
- Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption OptimizationNick Kanopoulos. 2 [doi]
- Low-Voltage Embedded RAMs - Current Status and Future TrendsKiyoo Itoh, Kenichi Osada, Takayuki Kawahara. 3-15 [doi]
- Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse BiasingCarlo Dallavalle. 16 [doi]
- Leakage in CMOS Circuits - An IntroductionDomenik Helms, Eike Schmidt, Wolfgang Nebel. 17-35 [doi]
- The Certainty of Uncertainty: Randomness in Nanometer DesignHongliang Chang, Haifeng Qian, Sachin S. Sapatnekar. 36-47 [doi]
- Crosstalk Cancellation for Realistic PCB BusesJihong Ren, Mark R. Greenstreet. 48-57 [doi]
- A Low-Power Encoding Scheme for GigaByte Video InterfacesSabino Salerno, Enrico Macii, Massimo Poncino. 58-68 [doi]
- Dynamic Wire Delay and Slew Metrics for Integrated Bus StructuresMarkus Tahedl, Hans-Jörg Pfleiderer. 69-78 [doi]
- Perfect 3-Limited-Weight Code for Low Power I/OMircea R. Stan, Yan Zhang. 79-89 [doi]
- A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System BusesClaudia Kretzschmar, Torsten Bitterlich, Dietmar Müller. 90-99 [doi]
- Performance Metric Based Optimization ProtocolXavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne. 100-109 [doi]
- Temperature Dependence in Low Power CMOS UDSM ProcessB. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne. 110-118 [doi]
- Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV TechniquesMauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti. 119-128 [doi]
- High Yield Standard Cell Libraries: Optimization and ModelingNicola Dragone, Michele Quarantelli, Massimo Bertoletti, Carlo Guardiani. 129-137 [doi]
- A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital CircuitsGabriella Trucco, Giorgio Boselli, Valentino Liberali. 138-147 [doi]
- Sleepy Stack Reduction of Leakage PowerJun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger. 148-158 [doi]
- A Cycle-Accurate Energy Estimator for CMOS Digital CircuitsEunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae. 159-168 [doi]
- Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier ArchitecturesChristian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine. 169-178 [doi]
- Reducing Cross-Talk Induced Power Consumption and DelayAndré K. Nieuwland, Atul Katoch, Maurice Meijer. 179-188 [doi]
- Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder CellIlham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre. 189-197 [doi]
- Leakage Power Analysis and Comparison of Deep Submicron Logic GatesGeoff Merrett, Bashir M. Al-Hashimi. 198-207 [doi]
- Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNSJie Ruan, Mark G. Arnold. 208-217 [doi]
- Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless ApplicationsArmin Wellig, Julien Zory, Norbert Wehn. 218-227 [doi]
- Register Isolation for Synthesizable Register FilesMatthias Müller, Andreas Wortmann, Dominik Mader, Sven Simon. 228-237 [doi]
- Discrete-Event Modeling and Simulation of Superscalar Microprocessor ArchitecturesCarlo Brandolese, William Fornaciari, Fabio Salice. 238-247 [doi]
- Design of High-Speed Low-Power Parallel-Prefix VLSI AddersGiorgos Dimitrakopoulos, P. Kolovos, P. Kalogerakis, Dimitris Nikolos. 248-257 [doi]
- GALSification of IEEE 802.11a Baseband ProcessorMilos Krstic, Eckhard Grass. 258-267 [doi]
- TAST Profiler and Low Energy Asynchronous Design MethodologyKamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin. 268-277 [doi]
- Low Latency Synchronization Through SpeculationD. J. Kinniment, Alexandre Yakovlev. 278-288 [doi]
- Minimizing the Power Consumption of an Asynchronous MultiplierYijun Liu, Stephen B. Furber. 289-300 [doi]
- A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode ModelingTobias Bjerregaard, Shankar Mahadevan, Jens Sparsø. 301-310 [doi]
- L0 Cluster Synthesis and Operation ShufflingMurali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck. 311-321 [doi]
- On Combined DVS and Processor EvaluationAnders Brødløs Olsen, Finn Büttner, Peter Koch. 322-331 [doi]
- A Multi-level Validation Methodology for Wireless Network ApplicationsChristos Drosos, Labros Bisdounis, Dimitris Metafas, Spyros Blionas, Anna Tatsaki. 332-341 [doi]
- SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic LevelEric Senn, Johann Laurent, Nathalie Julien, Eric Martin. 342-351 [doi]
- Run-Time Software Monitor of the Power Consumption of Wireless Network Interface CardsEmanuele Lattanzi, Andrea Acquaviva, Alessandro Bogliolo. 352-361 [doi]
- Towards a Software Power Cost Analysis Framework Using Colored Petri NetMeuse N. Oliveira Jr., Paulo Romero Martins Maciel, Raimundo S. Barreto, Fernando F. Carvalho. 362-371 [doi]
- A 260ps Quasi-static ALU in 90nm CMOSFrancesco Pessolano, R. I. M. P. Meijer. 372-380 [doi]
- Embedded EEPROM Speed Optimization Using System Power Supply ResourcesJean Michel Daga, Caroline Papaix, Marylene Combe, Emmanuel Racape, Vincent Sialelli. 381-391 [doi]
- Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area ConsumptionStephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel. 392-401 [doi]
- A Predictive Synchronizer for Periodic Clock DomainsUri Frank, Ran Ginosar. 402-412 [doi]
- Power Supply Net for Adiabatic CircuitsJürgen Fischer, Ettore Amirante, Agnese Bargagli-Stoffi, Philip Teichmann, Dominik Gruber, Doris Schmitt-Landsiedel. 413-422 [doi]
- A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOIKazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada. 423-432 [doi]
- Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power DeliveryJingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan. 433-441 [doi]
- An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical DesignYin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan. 442-452 [doi]
- Wirelength Reduction Using 3-D Physical DesignIdris Kaya, Silke Salewski, Markus Olbrich, Erich Barke. 453-462 [doi]
- On Skin Effect in On-Chip InterconnectsDaniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors. 463-470 [doi]
- A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed CircuitsDelong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev. 471-480 [doi]
- A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic ProcessorsMarco Bucci, Michele Guglielmo, Raimondo Luzzi, Alessandro Trifiletti. 481-490 [doi]
- A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software DesignUlrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger. 491-500 [doi]
- The Impact of Low-Power Techniques on the Design of Portable Safety-Critical SystemsAthanasios Kakarountas, Vassilis Spiliotopoulos, Spiridon Nikolaidis, Constantinos E. Goutis. 501-509 [doi]
- Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded SystemsDavid Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris. 510-520 [doi]
- PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip ArchitecturesGianluca Palermo, Cristina Silvano. 521-531 [doi]
- Power Consumption of Performance-Scaled SIMD ProcessorsAnteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat. 532-540 [doi]
- Low Effort, High Accuracy Network-on-Chip Power Macro ModelingAndrea Bona, Vittorio Zaccaria, Roberto Zafalon. 541-552 [doi]
- Exploiting Dynamic Workload Variation in Offline Low Energy Voltage SchedulingLap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu. 553-563 [doi]
- Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless ReceiversAna Rusu, Alexei Borodenkov, Mohammed Ismail, Hannu Tenhunen. 564-573 [doi]
- Power Aware Dividers in FPGAGustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo. 574-584 [doi]
- A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip BusesZahid Khan, Tughrul Arslan, Ahmet T. Erdogan. 585-592 [doi]
- The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing PlatformsNikolaos Vassiliadis, A. Chormoviti, Nikolaos Kavvadias, Spiridon Nikolaidis. 593-602 [doi]
- Low Power Co-design Tool and Power Optimization of Schedules and Memory SystemPatricia Guitton-Ouhamou, Hanene Ben Fradj, Cécile Belleudy, Spiridon Nikolaidis. 603-612 [doi]
- Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip PlatformKostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis. 613-622 [doi]
- Enhancing GALS Processor Performance Using Data Classification Based on Data LatencySonia López, Oscar Garnica, José Manuel Colmenar. 623-632 [doi]
- Application Analysis with Integrated Identification of Complex Instructions for Configurable ProcessorsNikolaos Kavvadias, Spiridon Nikolaidis. 633-642 [doi]
- Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded SystemsAmjad Mohsen, Richard Hofmann. 643-651 [doi]
- Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-PathMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis. 652-661 [doi]
- Power Estimation for Ripple-Carry Adders with Correlated Input DataKenny Johansson, Oscar Gustafsson, Lars Wanhammar. 662-674 [doi]
- LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNSMark G. Arnold. 675-684 [doi]
- Low Level Adaptive Frequency in Synthesis of High Speed Digital CircuitsLeonardo Valencia. 685-690 [doi]
- A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued LogicMyeong-Hoon Oh, Dong-Soo Har. 691-700 [doi]
- Pipelines in Dynamic Dual-Rail CircuitsJing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun. 701-710 [doi]
- Optimum Buffer Size for Dynamic Voltage ProcessorsAli Manzak, Chaitali Chakrabarti. 711-721 [doi]
- Design Optimization with Automated Cell GenerationA. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne. 722-731 [doi]
- A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation ToolFabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis. 732-741 [doi]
- A Novel Constant-Time Fault-Secure Binary CounterDimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis. 742-749 [doi]
- Buffer Sizing for Crosstalk Induced Delay UncertaintyDimitrios Velenis, Eby G. Friedman. 750-759 [doi]
- Optimal Logarithmic Representation in Terms of SNR BehaviorPanagiotis D. Vouzis, Vassilis Paliouras. 760-769 [doi]
- A New Logic Transformation Method for Both Low Power and High TestabilityY.-S. Son, J. W. Na. 770-779 [doi]
- Energy-Efficient Hardware Architecture for Variable N-point 1D DCTAndrew Kinane, Valentin Muresan, Noel E. O Connor, Noel Murphy, Seán Marlow. 780-788 [doi]
- Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched CircuitsStephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel. 789-798 [doi]
- A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation EnvironmentAlexander Maili, Damian Dalton, Christian Steger. 799-808 [doi]
- Modeling Temporal and Spatial Power Supply Voltage Variation for Timing AnalysisHoward Chen, Daniel L. Ostapko. 809-818 [doi]
- On Timing and Power Consumption in Inductively Coupled On-Chip InterconnectsTudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner. 819-828 [doi]
- Signal Sampling Based Transition Modeling for Digital Gates CharacterizationAlejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero, Enrique Ostúa. 829-837 [doi]
- Physical Extension of the Logical Effort ModelB. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne. 838-848 [doi]
- An Extended Transition Energy Cost Model for Buses in Deep Submicron TechnologiesPeter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Andersson, Atila Alvandpour, Christer Svensson. 849-858 [doi]
- Moment-Based Estimation of Switching Activity for Correlated DistributionsAlberto García Ortiz, Tudor Murgan, Manfred Glesner. 859-868 [doi]
- Table-Based Total Power Consumption Estimation of Memory Arrays for ArchitectsMinh Quang Do, Per Larsson-Edefors, Lars Bengtsson. 869-878 [doi]
- A Physically Oriented Model to Quantify the Noise-on-Delay EffectTobias Gemmeke, Tobias G. Noll. 879-888 [doi]
- Noise Margin in Low Power SRAM CellsStefan Cserveny, Jean-Marc Masgonty, Christian Piguet. 889-898 [doi]
- Delay Evaluation of High Speed Data-Path Circuits Based on Threshold LogicPeter Celinski, Derek Abbott, Sorin Cotofana. 899-906 [doi]