Abstract is missing.
- Delay dependent power optimisation of combinational circuits using AND-Inverter graphsRashmi Mehrotra, Tom English, Emanuel M. Popovici, Michel P. Schellekens. 9-14 [doi]
- Simultaneous co-design of distributed on-chip power supplies and decoupling capacitorsSelçuk Köse, Eby G. Friedman. 15-18 [doi]
- Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variationNa Gong, Ramalingam Sridhar. 19-24 [doi]
- A run-time distributed cooperative approach to optimize power consumption in MPSoCsImen Mansouri, Fabien Clermidy, Pascal Benoit, Lionel Torres. 25-30 [doi]
- Highly programmable switched-capacitor filters using biquads with nonuniform internal clocksOliver E. Gysel, Paul J. Hurst, Stephen H. Lewis. 33-38 [doi]
- A digitally self-calibrated low-noise 7-bit folding A/D converterMinah Kwon, Dahsom Kim, Daeyun Kim, Junho Moon, Minkyu Song. 39-43 [doi]
- A high-resolution and fast-conversion readout circuit for differential capacitive sensorsJong-Kwan Woo, Hyunjoong Lee, SungHo Ahn, Suhwan Kim. 44-47 [doi]
- Jitter transfer function model and VLSI jitter filter circuitsHongjiang Song, Jianan Song, Aritra Dey, Yan Song. 48-51 [doi]
- A holistic view on low power designThomas Büchner. 55 [doi]
- A 10B 200MHz pipeline ADC with minimal feedback penalty and 0.35pJ/conversion-stepGang Chen, Yifei Luo, Jiayin Tian, Kuan Zhou. 59-64 [doi]
- High speed recursion-free CORDIC architectureShakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham. 65-70 [doi]
- A 1 ppm/°C bandgap voltage reference with new second-order Taylor curvature compensationRalph Oberhuber, Rahul Prakash, Vadim Ivanov. 71-76 [doi]
- Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjusterDongsuk Shin, Joo-Hwan Cho, Young-Jung Choi, Byong-Tae Chung. 79-82 [doi]
- A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOSSang-Ho Kim, Hyung-Min Park, Tae-Ho Kim, Jin-Ku Kang, Jin-Ho Kim, Jae-Youl Lee, Yoon Kyung Choi, Myunghee Lee. 84-87 [doi]
- A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2Jae Wook Yoo, Tae-Ho Kim, Dong-Kyun Kim, Jin-Ku Kang. 88-91 [doi]
- Low-power SOC implementation: What you need to knowKaijian Shi. 95 [doi]
- System-level exploration of mesh-based NoC architectures for multimedia applicationsNing Ma, Zhonghai Lu, Zhibo Pang, Li-Rong Zheng. 99-104 [doi]
- A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessorSoonwoo Choi, Jason J. K. Park, Moonmo Koo, Daewoong Kim, Soo-Ik Chae. 105-108 [doi]
- A high-efficiency reconfigurable 2-D Discrete Wavelet Transform engine for JPEG2000 implementation on next generation digital camerasXin Zhao, Ying Yi, Ahmet T. Erdogan, Tughrul Arslan. 109-112 [doi]
- Orthogonal shift level comparison reuse for structuring element shape independent VLSI-Architectures of 2D morphological operationsMarkus Holzer, Ruben Bartholomä, Thomas Greiner, Wolfgang Rosenstiel. 113-118 [doi]
- Case study: Runtime reduction of a buffer insertion algorithm using GPU parallel programmingWon Ha Choi, Xun Liu. 121-126 [doi]
- Unleash the parallelism of 3DIC partitioning on GPGPUHsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou. 127-132 [doi]
- Routability-driven RDL routing with pin reassignmentJin-Tai Yan, Ke-Chyuan Chen, Zhi-Wei Chen. 133-138 [doi]
- Statistical electro-thermal analysis with high compatibility of leakage power modelsHuai-Chung Chang, Pei-Yu Huang, Ting-Jung Li, Yu-Min Lee. 139-144 [doi]
- Variation-tolerant design of D-flipflopsHiroki Sunagawa, Hidetoshi Onodera. 147-151 [doi]
- High speed and low power transceiver design with CNFET and CNT bundle interconnectYoung Bok Kim, Yong-Bin Kim. 152-157 [doi]
- NBTI-aware statistical timing analysis frameworkSangwoo Han, Juho Kim. 158-163 [doi]
- Implementation of a hardware-efficient EEG processor for brain monitoring systemsChiu-Kuo Chen, Ericson Chua, Shao-Yen Tseng, Chih-Chung Fu, Wai-Chi Fang. 164-168 [doi]
- Design and analysis of an advanced static blocked multithreading architectureYe Lu, Sakir Sezer, John V. McCanny. 169-173 [doi]
- A Folding Strategy for SAT solvers based on Shannon's expansion theoremSiwat Saibua, Po-Yu Kuo, Dian Zhou, Ming-e Jing. 177-181 [doi]
- TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architecturesDan Liu 0003, Yi Feng, Jingjin Zhou, Dong Tong, Xu Cheng, Keyi Wang. 182-187 [doi]
- Expandable MDC-based FFT architecture and its generator for high-performance applicationsBu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou. 188-192 [doi]
- A SystemCAMS extension for the simulation of non-linear circuitsThomas Uhle, Karsten Einwich. 193-198 [doi]
- An automated control code generation approach for the SegBus platformMoazzam Fareed Niazi, Tiberiu Seceleanu, Hannu Tenhunen. 199-204 [doi]
- From Film to Silicon: The Migration of Document Archiving TechnologyP. R. Mukund. 205 [doi]
- Power noise suppression technique using active decoupling capacitor for TSV 3D integrationTien-Hung Lin, Po-Tsang Huang, Wei Hwang. 209-212 [doi]
- Estimation of maximum application-level power supply noiseTung-Yeh Wu, Sriram Sambamurthy, Jacob A. Abraham. 213-218 [doi]
- Simultaneous voltage island generation and floorplanningHoung-Yi Li, Iris Hui-Ru Jiang, Hung-Ming Chen. 219-223 [doi]
- Footer voltage feedforward domino technique for wide fan-in dynamic logicRahul Singh, Ahreum Kim, Suhwan Kim. 224-229 [doi]
- Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuitsAnkitchandra Shah, Hamid Mahmoodi. 230-235 [doi]
- Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCsYu-Jen Huang, Yun-Chao You, Jin-Fu Li. 236-240 [doi]
- Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate arrayYuji Aoyama, Minoru Watanabe. 243-247 [doi]
- A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluationTakashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato. 248-253 [doi]
- Binary object recognition system on FPGA with bSOMKofi Appiah, Andrew Hunter, Patrick Dickinson, Hongying Meng. 254-259 [doi]
- Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable arrayNaifeng Jing, Weifeng He, Zhigang Mao. 260-265 [doi]
- Design of a link-controller architecture for multiple serial link protocolsLei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija. 266-271 [doi]
- High-Performance random data lookup for network processingXin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns. 272-277 [doi]
- A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifierJiaping Hu, Yong-Bin Kim, Joseph Ayers. 281-284 [doi]
- A CMOS low-power low-offset and high-speed fully dynamic latched comparatorHeungJun Jeon, Yong-Bin Kim. 285-288 [doi]
- A CMOS 6 bit 250MS/s A/D converter with input voltage range detectorsKwang Yoon, Won Kim. 289-292 [doi]
- Clock buffer with duty cycle correctorShao-Ku Kao, Yong-De You. 293-296 [doi]
- A 70dB SNDR 10-MHz BW hybrid delta-sigma/pipeline ADC in 0.18-µm CMOSXiong Liu, Alan N. Willson Jr.. 297-300 [doi]
- 8Gbps high-speed I/O transmitter with scalable speed, swing and equalization levelsMohammed Younus, Hongjiang Song. 301-304 [doi]
- Run-time configuration prefetching to reduce the overhead of dynamically reconfigurationBinbin Wu, Like Yan, Yuan Wen, Tianzhou Chen. 305-308 [doi]
- A multi-channel frequency detection and monitoring systemMohammed Abdallah, Omar S. Elkeelany. 309-312 [doi]
- Process technology and design parameter impact on SRAM Bit-Cell Sleep effectivenessGururaj Shamanna, Bhunesh S. Kshatri, Raja Gaurav, Y. S. Tew, P. Marfatia, Y. Raghavendra, V. Naik. 313-316 [doi]
- Interconnect system compression analysis for multi-core architecturesJiangjiang Liu, Jianyong Zhang, Nihar R. Mahapatra. 317-320 [doi]
- Fan-in sensitive low power dynamic circuits performance statistical characterizationJinhui Wang, Na Gong, Wuchen Wu, Ligang Hou. 321-325 [doi]
- Energy efficient computation with self-adaptive single-ended body biasSenthil Jayapal, Jan Stuijt, Jos Huisken, Yiannos Manoli. 326-329 [doi]
- Power minimization methodology for VCTL topologiesOsman Kubilay Ekekon, Samed Maltabas, Martin Margala, Ugur Çilingiroglu. 330-333 [doi]
- Hybrid MOSFET/CNFET based power gating structureKyung Ki Kim, Haiqing Nan, Ken Choi. 334-338 [doi]
- Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologiesAnuj Pushkarna, Sajna Raghavan, Hamid Mahmoodi. 339-342 [doi]
- A BDD-based approach to design power-aware on-line detectors for digital circuitsGopal Paul, Santosh Biswas, Chittaranjan A. Mandal, Bhargab B. Bhattacharya. 343-346 [doi]
- An efficient VLSI architecture for extended variable block sizes motion estimationWeifeng He, Weiwei Chen, Zhigang Mao. 347-350 [doi]
- A multimedia content generation methodology in support to SOC decoder development and validationTuyet-Trang Lam, Ricardo Citro. 351-354 [doi]
- Effect of a polywell leometry on a CMOS photodiode arrayPaul V. Jansz-Drávetzky, Steven Hinckley, Graham Wild. 355-358 [doi]
- MMPI: A flexible and efficient multiprocessor message passing interface for NoC-based MPSoCFangfa Fu, Siyue Sun, Xin'an Hu, Junjie Song, Jinxiang Wang, Mingyan Yu. 359-362 [doi]
- A method for efficient NoC test scheduling using deterministic routingRana Farah, Haidar Harmanani. 363-366 [doi]
- Flow oriented routing for NOCSEverton Carara, Fernando Moraes. 367-370 [doi]
- A globally-interconnected modular CMP system with communication on the flyMarek Tudruj, Lukasz Masko. 371-374 [doi]
- Energy and delay-aware mapping for real-time digital processing system on network on chip platformsYiou Chen, JianHao Hu, Gengsheng Chen, Xiang Ling. 375-378 [doi]
- Thermal modelling of 3D multicore systems in a flip-chip packageKameswar Rao Vaddina, Tamoghna Mitra, Pasi Liljeberg, Juha Plosila. 379-383 [doi]
- Efficient multicasting scheme for irregular mesh-based NoCsXiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu 0016. 384-387 [doi]
- Towards formal system-level verification of security requirements during hardware/software codesignJohannes Loinig, Christian Steger, Reinhold Weiss, Ernst Haselsteiner. 388-391 [doi]
- Thermal via planning for temperature reduction in 3D ICsJin-Tai Yan, Yu-Cheng Chang, Zhi-Wei Chen. 392-395 [doi]
- A design procedure of predictive RF MOSFET model for compatibility with ITRSSinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera. 396-399 [doi]
- What You Need to Know About Patent LitigationJo Dale Carothers. 403 [doi]
- A novel architectural approach for control architectures in RF transceiversSiegfried Brandstätter, Burkhard Neurauter, Mario Huemer. 407-412 [doi]
- A mixed-signal timing circuit in 90nm CMOS for energy detection IR-UWB receiversQin Zhou, Jia Mao, Zhuo Zou, Fredrik Jonsson, Li-Rong Zheng. 413-416 [doi]
- A novel architecture for discrete chaotic signal generatorsQihang Shi, Xinzhi Xu, Jingbo Guo. 417-422 [doi]
- Quality-driven SoC architecture synthesis for embedded applicationsLech Józwiak. 425-426 [doi]
- DyML: Dynamic Multi-Level flow control for Networks on ChipWen-Chung Tsai, Ying-Cherng Lan, Sao-Jie Chen, Yu Hen Hu. 429-434 [doi]
- A prediction-based, data Migration Algorithm for hybrid Architecture NoC systemsJon Nafziger, Annie Avakian, Ranga Vemuri. 435-440 [doi]
- FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-ChipChaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang. 441-446 [doi]
- Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoCAnkit More, Baris Taskin. 447-452 [doi]
- A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off schemeBai Na, Xuan Chen, Yang Jun, Longxin Shi. 455-460 [doi]
- Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS FlashShantanu Rajwade, Wing-Kei S. Yu, Sarah Q. Xu, Tuo-Hung Hou, G. Edward Suh, Edwin Kan. 461-466 [doi]
- Handling shared variable synchronization in multi-core Network-on-Chips with distributed memoryXiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen. 467-472 [doi]
- Low-energy configurable syndrome/chien search multi-channel Reed Solomon decoderHamed Salah, Hazem A. Ahmed, Tallal Elshabrawy, Hossam A. H. Fahmy. 473-478 [doi]
- Run-time communication bypassing for energy-efficient, low-latency per-core DVFS on Network-on-ChipLiang Guang, Ethiopia Nigussie, Hannu Tenhunen. 481-486 [doi]
- Comparative performance evaluation of wireless and optical NoC architecturesSujay Deb, Kevin Chang, Amlan Ganguly, Partha Pratim Pande. 487-492 [doi]
- Hermes-AA: A 65nm asynchronous NoC router with adaptive routingJulian J. H. Pontes, Matheus T. Moreira, Fernando Moraes, Ney Calazans. 493-498 [doi]
- Power analysis for Asynchronous CLICHÉ Network-on-ChipMohamed A. Abd El ghany, Gursharan Reehal, Darek Korzec, Mohammed Ismail. 499-504 [doi]
- Way-load balancing scheme for mobile cache LRU replacementSatish Raghunath, Naveen Davanam, Lakshmi Deepika Bobbala, Byeong Kil Lee. 507-512 [doi]
- Exploiting large on-chip memory space through data recomputationHakduran Koc, Mahmut T. Kandemir, Ehat Ercanli. 513-518 [doi]
- Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operationKoji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto. 519-524 [doi]