| 6 | -- | 0 | Yervant Zorian. Wider Coverage |
| 12 | -- | 14 | Scott Davidson, Justin E. Harlow III. Guest Editors Introduction: Benchmarking for Design and Test |
| 15 | -- | 17 | Justin E. Harlow III. Overview of Popular Benchmark Sets |
| 18 | -- | 21 | Rohit Kapur, Cy Hay, Thomas W. Williams. The Mutating Metric for Benchmarking Test |
| 22 | -- | 32 | Giulio Gorla, Eduard Moser, Wolfgang Nebel, Eugenio Villar. System Specification Experiments on a Common Benchmark |
| 34 | -- | 42 | Chouki Aktouf, Hérvé Fleury, Chantal Robach. Inserting Scan at the Behavioral Level |
| 44 | -- | 53 | Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero. RT-Level ITC 99 Benchmarks and First ATPG Results |
| 54 | -- | 59 | Luis Basto. First Results of ITC 99 Benchmark Circuits |
| 60 | -- | 71 | Sujit Dey, Debashis Panigrahi, Li Chen, Clark N. Taylor, Krishna Sekar, Pablo Sanchez. Using a Soft Core in a SoC Design: Experiences with picoJava |
| 72 | -- | 77 | Chien-Nan Jimmy Liu, Jing-Yang Jou. An Automatic Controller Extractor for HDL Descriptions at the RTL |
| 78 | -- | 85 | Axel Jantsch, Shashi Kumar, Ahmed Hemani. A Metamodel for Studying Concepts in Electronic System Design |
| 86 | -- | 94 | Rolf Clauberg, Peter Buchmann, Andreas Herkersdorf, David J. Webb. Design Methodology for a Large Communication Chip |
| 95 | -- | 105 | Mauro Bertacchi, Alessandro De Gloria, Daniele Grosso, Mauro Olivieri. Semicustom Design of an IEEE 1394-Compliant Reusable IC Core |
| 106 | -- | 115 | Pramodchandran N. Variyam, Abhijit Chatterjee. Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling |
| 116 | -- | 124 | Seung H. Hwang, Gwan S. Choi. A Reliability Testing Environment for Off-the-Shelf Memory Subsystems |
| 126 | -- | 132 | . A D&T Roundtable: Test Resource Partitioning |
| 133 | -- | 135 | . Panel Summaries |
| 136 | -- | 137 | Mukund Modi. TTTC Reports on Recent Standards Activities |
| 142 | -- | 144 | Franc Brglez. The Scientific Method and Design and Test |