External Links

    Journal: IEEE Design & Test of Computers

    Volume 2, Issue 6

    13 -- 26John Paul Shen, Wojciech Maly, F. Joel Ferguson. Inductive Fault Analysis of MOS Integrated Circuits
    27 -- 35Peter Odryna, Andrzej J. Strojwas. PROD: A VLSI Fault Diagnosis System
    36 -- 43Kofi E. Torku, Dave A. Kiesling. Noise Problems in Testing VLSI Hardware
    44 -- 49Tim Moore, Stephen Garner. Autoprobing on the L200 Functional Tester
    50 -- 56David F. Farnholtz. Operational Life Testing of Electronic Components
    57 -- 62Wayne Ponik. Teradyne's J967 VLSI Test System: Getting VLSI to the Market on Time

    Volume 2, Issue 5

    17 -- 26Osamu Karatsu, Tamio Hoshino, Makoto Endo, Hitoshi Kitazawa, Tohru Adachi, Kazuhiro Ueda. An Integrated Design Automation System for VLSI Circuits
    27 -- 34Takao Uehara. A Knowledge-Based Logic Design System
    35 -- 42Kiyoshi Enomoto, Shunichiro Nakamura, Takuji Ogihara, Shinichi Murai. LORES-2: A Logic Reorganization System
    43 -- 53Tokinori Kozawa, Hidekazu Terai. Research in Design Automation for VLSI Layout
    54 -- 60Shigehiro Funatsu, Masato Kawai. An Automatic Test-Generation System for Large Digital Circuits
    61 -- 73Nobuhiko Koike, Kenji Ohmori, Tohru Sasaki. HAL: A High-Speed Logic Simulation Machine
    74 -- 82Norio Kuji, Teruo Tamama, Takao Yano. A Fully-Automated Electron Beam Test System for VLSI Circuits
    83 -- 89Tohru Kazamaki. Milestones of New-Generation ATE
    112 -- 115J. Daniel Nash. New Products Design
    116 -- 117Conrad Zagwyn. New Products Test
    125 -- 127Robert E. Anderson. Book Reviews

    Volume 2, Issue 4

    22 -- 32Aart J. de Geus, William W. Cohen. A Rule-Based System for Optimizing Combinational Logic
    33 -- 43Ted J. Kowalski, David J. Geiger, Wayne H. Wolf, Wolfgang Fichtner. The VLSI Design Automation Assistant: From Algorithms to Silicon
    44 -- 55Robert A. Mueller, Joseph Varghese. Knowledge-Based Code Selection Methods in Retargetable Microcode Synthesis
    56 -- 68Magdy S. Abadir, Melvin A. Breuer. A Knowledge-Based System for Designing Testable VLSI Chips
    69 -- 77A. Jesse Wilkinson. MIND: An inside Look at an Expert System for Electronic Diagnosis
    78 -- 86Tariq Samad, Stephen W. Director. Natural-Language Interface for CAD: A First Step
    93 -- 96J. Daniel Nash. New Products Design
    97 -- 99Conrad Zagwyn. New Products Test

    Volume 2, Issue 3

    20 -- 28Gordon H. Bowers Jr., Bruce G. Pratt. Low-Cost Testers: Are They Really Low Cost?
    29 -- 34Anthony P. van den Heuvel, Noshir F. Khory. A Basis for Setting Burn-in Yield Criteria
    35 -- 44John R. Day. A Fault-Driven, Comprehensive Redundancy Algorithm
    45 -- 55Dean Bandes. Exploratory Data Analysis for Semiconductor Manufacturing
    56 -- 63Douglas K. Shirachi. Codec Testing Using Synchronized Analog And Digital Signals
    64 -- 72Thomas G. Szymanski, Christopher J. Van Wyk. Goalie: A Space Efficient System for VLSI Artwork Analysis
    101 -- 103Conrad Zagwyn. New Products Test
    104 -- 107J. Daniel Nash. New Products Design
    110 -- 0Robert E. Anderson. Book Reviews

    Volume 2, Issue 2

    21 -- 28Edward J. McCluskey. Built-In Self-Test Techniques
    29 -- 36Edward J. McCluskey. Built-In Self-Test Structures
    37 -- 48Robert P. Treuer, Hideo Fujiwara, Vinod K. Agarwal. Implementing a Built-In Self-Test PLA Design
    50 -- 58Richard J. Illman. Self-Tested Data Flow Logic: A New Approach
    59 -- 63Thomas W. Williams. Test Length in a Self-Testing Environment
    64 -- 71R. Gary Daniels, William C. Bruce. Built-In Self-Test Trends in Motorola Microprocessors
    75 -- 81Carolyn E. Tajnai. Fred Terman, the Father of Silicon Valley
    82 -- 87Donald L. Lacy, Lawrence A. Drenan. Implementing and Managing a CAD System Based on Vendor-Supplied Tools
    96 -- 100Conrad Zagwyn. New Products Test
    101 -- 103J. Daniel Nash. New Products Design
    106 -- 115A. Richard Newton, Donald O. Pederson, Alberto L. Sangiovanni-Vincentelli. Design Aids for VLSI: A Perspective Revisited
    118 -- 119Robert E. Anderson. Book Reviews

    Volume 2, Issue 1

    19 -- 30John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor. The Magic VLSI Layout System
    31 -- 37Todd J. Wagner. Hierarchical Layout Verification
    38 -- 44Sunil K. Jain, Vishwani D. Agrawal. Statistical Fault Analysis
    45 -- 54Louis I. Steinberg, Tom M. Mitchell. The Redesign System: A Knowledge-Based Approach to VLSI CAD
    55 -- 62Karl J. Lieberherr. Toward a Standard Hardware Description Language
    63 -- 69John D. Crawford. EDIF: A Mechanism for the Exchange of Design Information
    82 -- 86J. Daniel Nash. New Products Design
    87 -- 91Conrad Zagwyn. New Products Test
    94 -- 95Robert E. Anderson. Book Reviews
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