Journal: IEEE Transactions on Computers

Volume 30, Issue 9

619 -- 634K. C. Smith. The Prospects for Multivalued Logic: A Technology and Applications View
635 -- 643Tsutomu Sasao. Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays
644 -- 652Hans G. Kerkhoff, Marius L. Tervoert. Multiple-Valued Logic Charge-Coupled Devices
653 -- 661Marc Davio, Jean-Pierre Deschamps. Synthesis of Discrete Functions Using I:::2:::L Technology
662 -- 666Tich T. Dao. SEC-DED Nonbinary Code for Fault-Torelant Byte-Organized Memory Implemented with Quaternary Logic
666 -- 671Waldo C. Kabat, Anthony S. Wojcik. On the Design of 4-Valued Digital Systems
671 -- 674A. D. Singh, F. Gail Gray, James R. Armstrong. Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules
674 -- 679Gardner Pomper, James R. Armstrong. Representation of Multivalued Functions Using the Direct Cover Method
679 -- 690Craig S. Holt, James E. Smith. Diagnosis of Systems with Asymmetric Invalidation
691 -- 699John H. Zurawski, J. B. Gosling. Design of High-Speed Digital Divider Units
699 -- 703S. Dormido, M. A. Canto. Synthesis of Generalized Parallel Counters

Volume 30, Issue 8

525 -- 536Jerry R. Van Aken, Gregory L. Zick. The Expression Processor: A Pipelined, Multiple-Processor Architecture
537 -- 545Gian Carlo Bongiovanni, C. K. Wong. Tree Search in Major/Minor Loop Magnetic Bubble Memories
545 -- 556Suchai Thanawastien, Victor P. Nelson. Interference Analysis of Shuffle/Exchange Networks
556 -- 562Hideo Fujiwara. On Closedness and Test Complexity of Logic Circuits
563 -- 571Thirumalai Sridhar, John P. Hayes. A Functional Approach to Testing Bit-Sliced Microprocessors
572 -- 581Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki. A Layout System for the Random Logic Portion of an MOS LSI Chip
582 -- 587Vishwani D. Agrawal. An Information Theoretic Approach to Digital Fault Testing
587 -- 590James R. Armstrong, F. Gail Gray. Fault Diagnosos in a Boolean ::::n:::: Cube Array of Microprocessors
590 -- 596Jon T. Butler. Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms
596 -- 600Alan B. Hayes. Stored State Asynchronous Sequential Circuits
600 -- 604Yashwant K. Malaiya, Stephen Y. H. Su. Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults
604 -- 606George Markowsky. Syndrome-Testability Can be Achieved by Circuit Modification
606 -- 608Jacob Savir. Syndrome-Testing of Syndrome-Untestable Combinational Circuits
608 -- 609Jack Worlton. Comments on Parallelism and Representation Problems in Distributed Systems
609 -- 613Jim B. Surjaatmadja. An Algebra for Switching Circuits

Volume 30, Issue 7

460 -- 477Scott Davidson, David Landskov, Bruce Shriver, Patrick W. Mallett. Some Experiments in Local Microcode Compaction for Horizontal Machines
478 -- 490Joseph A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction
491 -- 504Mario Tokoro, Euji Tamura, Takashi Takizuka. Optimization of Microprograms
505 -- 513John A. Stankovic. The Types and Interactions of Vertical Migrations of Functions in a Multilevel Interpretive System
513 -- 519Andries van Dam, Mario Barbacci, Constantine Halatsis, J. Joosten, M. Letheren. Simulation of a Horizontal Bit-Sliced Processor Using the ISPS Architecture Simulation Facility
519 -- 523Glenford J. Myers, David G. Hocker. The Use of Software Simulators in the Testing and Debugging of Microprogram Logic

Volume 30, Issue 6

373 -- 395Takanobu Baba, Hiroshi Hagiwara. The MPG System: A Machine-Independent Efficient Microprogram Generator
396 -- 405D. T. Lee, Hsu Chang, C. K. Wong. An On-Chip Compare/Steer Bubble Sorter
405 -- 413Jacques Labetoulle, Guy Pujolle. HDLC Throughput and Response Time for Bidirectional Data Flow with Nonuniform Frame Sizes
414 -- 422Kyung-Yong Chwa, S. Louis Hakimi. On Fault Identification in Diagnosable Systems
423 -- 439Alice C. Parker, John J. Wallace. SLIDE: An I/O Hardware Descriptive Language
439 -- 442Makoto Imase, Masaki Itoh. Design to Minimize Diameter on Building-Block Network
443 -- 447Edward A. Snow, Daniel P. Siewiorek. Implementation and Performance Evaluation of Computer Families
447 -- 451Stephen H. Unger. Double-Edge-Triggered Flip-Flops
452 -- 0S. Prakash, V. V. Rao. Comments on Very Fast Fourier Transform Algorithms Hardware for Implementation
453 -- 454Irving S. Reed, Trieu-Kien Truong, Boonsieng Benjauthrit. Addendum to A New Hybrid Algorithm for Computing a Fast Discrete Fourier Transform
454 -- 0G. Persky, Bou Nin Tien, B. S. Ting. Comments on An Optimal Solution for the Channel-Assignment Problem
455 -- 0Ulrich Lauther. Additional Comments on An Optimal Solution for the Channel-Assignment Problem
455 -- 0Frank Rubin. Further Comments on An Optimal Solution for the Channel-Assignment Problem

Volume 30, Issue 5

305 -- 312Takao Uehara, William M. van Cleemput. Optimal Layout of CMOS Functional Arrays
312 -- 317Israel Koren, Yoram Maliniak. On Classes of Positive, Negative, and Imaginary Radix Number Systems
318 -- 324Wesley W. Chu, Guy Fayolle, David G. Hibbits. An Analysis of a Tandem Queueing System for Flow Control in Computer Networks
324 -- 332Chuan-lin Wu, Tse-Yun Feng. The Universality of the Shuffle-Exchange Network
332 -- 340David Nassimi, Sartaj Sahni. A Self-Routing Benes Network and Parallel Permutation Algorithms
341 -- 356Walid A. Abu-Sufah, David J. Kuck, Duncan H. Lawrie. On the Performance Enhancement of Paging Systems Through Program Analysis and Transformations
356 -- 358Se June Hong, Daniel L. Ostapko. A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks
359 -- 360Dusan M. Kodek. Conditions for the Existence of Fast Number Theoretic Transforms
361 -- 362Neil V. Murray. Some Observations on Equivalence Handling Methods
363 -- 366Andrzej Proskurowski. Minimum Broadcast Trees
366 -- 370Patrick Shen-Pei Wang. Finite-Turn Repetitive Checking Automata and Sequential/Parallel Matrix Languages
370 -- 372Angela Y. Wu, Azriel Rosenfeld. SIMD Machines and Cellular ::::d::::-Graph Automata

Volume 30, Issue 4

247 -- 253Ellis Horowitz, Alessandro Zorat. The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI
254 -- 264Shyue B. Wu, Ming T. Liu. A Cluster Structure as an Interconnection Network for Large Multimicrocomputer Systems
264 -- 273Larry D. Wittie. Communication Structures for Large Networks of Microcomputers
273 -- 282Daniel M. Dias, J. Robert Jump. Analysis and Simulation of Buffered Delta Networks
283 -- 291Mark A. Franklin. VLSI Performance Comparison of Banyan and Crossbar Communications Networks
291 -- 295Bruce W. Arden, Hikyu Lee. Analysis of Chordal Ring Network
296 -- 298Pen-Chung Yew, Duncan H. Lawrie. An Easily Controlled Network for Frequently Used Permutation
298 -- 301J. E. Wirsching, T. Kishi. CONET: A Connection Network Model

Volume 30, Issue 3

172 -- 181Lawrence Snyder. Formal Models of Capability-Based Protection Systems
182 -- 190Toshihide Ibaraki, Tsunehiko Kameda, Shunichi Toida. On Minimal Test Sets for Locating Single Link Failures in Networks
190 -- 206Daniel Gajski. An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines
207 -- 214Shahid H. Bokhari. On the Mapping Problem
215 -- 222Prabhakar Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
223 -- 225William F. McColl. Planar Crossovers
225 -- 229W. R. English. Synthesis of Finite State Algorithms in a Galois Field GF[p:::::::n:::::::]
229 -- 234Mamoru Tanaka, Shinji Ozawa, Shinsaku Mori. Rewritable Progammable Logic Array of Current Mode Logic
234 -- 237Sung Je Hong. Existence Algorithms for Synchronizing/Distinguishing Sequences
237 -- 240A. Sengupta, D. K. Chattopadhyay, A. Palit, A. K. Bandyopadhyay, A. K. Choudhury. Realization of Fault-Tolerant Machines - Linear Code Application
241 -- 0Gerhard Wustmann. Comments on Autocorrelation Function of Sequential ::::M::::-Bit Words Taken from an ::::N::::-Bit Shift Register (PN) Sequence

Volume 30, Issue 2

93 -- 100Gavriela Freund Lev, Nicholas Pippenger, Leslie G. Valiant. A Fast Parallel Algorithm for Routing in Permutation Networks
101 -- 107David Nassimi, Sartaj Sahni. Data Broadcasting in SIMD Computers
107 -- 115Leonard R. Marino. General Theory of Metastable Operation
116 -- 125Marc Davio. Kronecker Products and Shuffle Algebra
126 -- 134André Thayse. ::::P::::-Functions: A New Tool for the Analysis and Synthesis of Binary Programs
135 -- 140Leslie G. Valiant. Universality Considerations in VLSI Circuits
141 -- 144Robert D. Braun, Donald D. Givone. A Generalized Algorithm for Constructing Checking Sequences
144 -- 147Ayakannu Mathialagan, Nripendra N. Biswas. Bit Steering in the Minimization of Control Memory in Microprogrammed Digital Computers
147 -- 148Kevin Q. Brown. Comments on Algorithms for Reporting and Counting Geometric Intersections
148 -- 153Charles B. Silio Jr., James H. Pugsley, B. Albert Jeng. Control Memory Wort Width Optimization Using Multiple-Valued Circuits
153 -- 156Dharma P. Agrawal, Krishna K. Agarwal. Efficient Sorting with CCD s and Magnetic Bubble Memories
157 -- 0J. George Shanthikumar. Comments on The Buffer Behavior in Computer Communication Systems
157 -- 161F. J. Hill, R. E. Swanson, M. Masud, Zainalabedin Navabi. Structure Specification with a Procedural Hardware Description Language
161 -- 164Stephen R. McConnel, Daniel P. Siewiorek. Synchronization and Voting
164 -- 168Jan Gecsei, Jean-Paul Brassard. The Topology of Cellular Partitioning Networks

Volume 30, Issue 12

909 -- 0Taylor L. Booth. In Memoriam: Richard E. Merwin (1922-1981)
910 -- 914David Avis, Godfried T. Toussaint. An Optimal Algorithm for Determining the Visibility of a Polygon from an Edge
915 -- 922Gita Gopal, J. W. Wong. Delay Analysis of Broadcast Routing in Packet-Switching Networks
923 -- 933James R. Goodman, Carlo H. Séquin. Hypertree: A Multiprocessor Interconnection Topology
934 -- 947Howard Jay Siegel, Leah J. Siegel, Frederick C. Kemmerer, Philip T. Mueller Jr., Harold E. Smalley, S. Diane Smith. PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
947 -- 953Mark G. Karpovsky. An Approach for Error Detection and Error Correction in Distributed Systems Computing Numerical Functions
953 -- 959Stephen M. Walters, F. Gail Gray, Richard A. Thompson. Self-Diagnosing Cellular Implementations of Finite-State Machines
960 -- 965Raphael A. Finkel, Marvin H. Solomon. The Lens Interconnection Strategy
966 -- 973Yih-Chyun Jenq. Digital Convolution Algorithm for Pipelining Multiprocessor Systems
973 -- 977Sharad C. Seth, K. Narayanaswamy. A Graph Model for Pattern-Sensitive Faults in Random Access Memories
977 -- 982David Steinberg, Michael Rodeh. A Layout for the Shuffle-Exchange Network with ::::O(N:::2:::/::::log:::3/2:::::::N::::) Area
982 -- 985Dong S. Suk, Sudhakar M. Reddy. A March Test for Functional Faults in Semiconductor Random Access Memories
986 -- 988S. L. Hurst. Comments on Design of a Dynamically Programmable Logic Gate
989 -- 995Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya. Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits
996 -- 1000Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith. The Weighted Syndrome Sums Approach to VLSI Testing

Volume 30, Issue 11

823 -- 828Hideo Fujiwara, Kozo Kinoshita. A Design of Programmable Logic Arrays with Universal Tests
829 -- 833Wilfried Daehn, Joachim Mucha. A Hardware Approach to Self-Testing of Large Programmable Logic Arrays
833 -- 841R. Parthasarathy, Sudhakar M. Reddy. A Testable Design of Iterative Logic Arrays
842 -- 854Thirumalai Sridhar, John P. Hayes. Design of Easily Testable Bit-Sliced Systems
855 -- 865Vinod K. Agarwal, Andy S. F. Fung. Multiple Fault Testing of Large Circuits by Single Fault Test Sets
866 -- 875Edward J. McCluskey, Saied Bozorgui-Nesbat. Design for Autonomous Test
875 -- 884Jacob A. Abraham, Daniel Gajski. Design of Testable Structures Defined by Simple Loops
884 -- 888Robert W. Priester, James B. Clary. New Measures of Testability and Test Complexity for Linear Analog Failure Analysis
889 -- 898V. Visvanathan, Alberto L. Sangiovanni-Vincentelli. Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case
899 -- 904Richard Saeks, Alberto L. Sangiovanni-Vincentelli, V. Visvanathan. Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems

Volume 30, Issue 10

709 -- 715David Gelernter. A DAG-Based Algorithm for Prevention of Store-and-Forward Deadlock in Packet Networks
715 -- 733Douglas W. Clark, Butler W. Lampson, Kenneth A. Pier. The Memory System of a High-Performance Personal Computer
733 -- 742Simon S. Lam, Y. C. Luke Lien. Congestion Control of Packet Communication Networks by Input Buffer Limits - A Simulation Study
743 -- 758Tse-Yun Feng, Chuan-lin Wu. Fault-Diagnosis for a Class of Multistage Interconnection Networks
758 -- 771Nai-Kuan Tsao. Error Complexity Analysis of Algorithms for Matrix Multiplication and Matrix Chain Product
771 -- 780Janak H. Patel. Performance of Processor-Memory Interconnections for Multiprocessors
781 -- 786J. George Shanthikumar. On the Buffer Behavior with Poisson Arrivals, Priority Service, and Random Server Interruptions
787 -- 800C. V. Ramamoorthy, Benjamin W. Wah. An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
800 -- 810Bulent I. Dervisoglu, Donald J. Criscione. A Hard Progammable Control Unit Design Using VLSI Technology
811 -- 812Takeo Kanai. An Improvement of Reliability of Memory System with Skewing Reconfiguration
812 -- 0Allan Gottlieb. Comments on Concurrent Search and Insertion in AVL Trees
813 -- 818C. V. Ramamoorthy, Benjamin W. Wah. The Degradation in Memory Utilization Due to Dependencies

Volume 30, Issue 1

1 -- 17Eugen I. Muehldorf, Anil D. Savkar. LSI Logic Testing - An Overview
17 -- 23John P. Robinson, Martin Cohn. Counting Sequences
24 -- 40Mario Barbacci. Instruction Set Processor Specifications (ISPS): The Notation and Its Applications
41 -- 48Bryan D. Ackland, Neil Weste. The Edge Flag Algorithm - A Fill Method for Raster Scan Displays
48 -- 61Donald E. Thomas, Daniel P. Siewiorek. Measuring Designer Performance to Verify Design Automation Systems
61 -- 66Mark A. Franklin, Norman L. Soong. One-Dimensional Optimization on Multiprocessor Systems
67 -- 77Simeon C. Ntafos, S. Louis Hakimi. On Structured Digraphs and Program Testing
78 -- 0D. G. Maritsas, M. G. Hartley. Comments on Revision of the Buffer Length Derivation for a Modified ::::E::k::/D/::::1 System by Maritsas and Hartley
79 -- 81Ricardo E. Suarez, Oscar Chang, Vladimir Adam. Design of a Dynamically Programmable Logic Gate
81 -- 83Gerard G. L. Meyer. A Fault Diagnosis Algorithm for Asymmetric Modular Architectures
83 -- 86Michael L. Fredman. Observations Concerning the Complexity of a Class of On-Line Algebraic Problems