Journal: IEEE Transactions on Computers

Volume 42, Issue 9

1025 -- 1034P. David Fisher, Sheng-Fu Wu. Race-Free State Assignment for Synthesizing Large-Scale Asynchronous Sequential Logic Circuits
1035 -- 1044Mark G. Karpovsky, Saeed M. Chaudhry. Design of Self-Diagnostic Boards by Multiple Signature Analysis
1045 -- 1057William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu. The Effect of Code Expanding Optimizations on Instruction Cache Design
1058 -- 1065Jürgen Götze, Steffen Paul, Matthias Sauer. An Efficient Jacobi-like Algorithm for Parallel Eigenvalue Computation
1066 -- 1077Irith Pomeranz, Sudhakar M. Reddy. Classification of Faults in Synchronous Sequential Circuits
1078 -- 1088Jong Kim, Kang G. Shin. Deadlock-Free Fault-Tolerant Routing in Injured Hypercubes
1089 -- 1104Jehoshua Bruck, Robert Cypher, Ching-Tien Ho. Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
1105 -- 1120Patrick W. Dowd, Kalyani Bogineni, Khaled A. Aly, James A. Perreault. Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection
1121 -- 1131Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer. Optimal Configuring of Multiple Scan Chains
1132 -- 1135William A. Porter, Xiaoyan Zheng. A Nonbinary Neural Network Design
1136 -- 1141Yung-Yuan Chen, Shambhu J. Upadhyaya. Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
1141 -- 1146Chin-Liang Wang, Jung-Lung Lin. A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2^m)
1146 -- 1151Kien A. Hua, Lishing Liu, Jih-Kwon Peir. Designing High-Performance Processors Using Real Address Prediction
1152 -- 0Masakatu Morii, Kazuhiko Iwasaki. A Note on Aliasing Probability for Multiple Input Signature Analyzer

Volume 42, Issue 8

898 -- 912Julio Ortega, Alberto Prieto, Antonio Lloris-Ruíz, Francisco J. Pelayo. Generalized Hopfield Neural Network for Concurrent Testing
913 -- 923Jean Arlat, Alain Costes, Yves Crouzet, Jean-Claude Laprie, David Powell. Fault Injection and Dependability Evaluation of Fault-Tolerant Systems
924 -- 937Bapiraju Vinnakota, Niraj K. Jha. Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems
938 -- 949Sandeep N. Bhatt, Geppino Pucci, Abhiram G. Ranade, Arnold L. Rosenberg. Scattering and Gathering Messages in Networks of Processors
950 -- 961Yutaka Hata, Kyoichi Nakashima, Kazuharu Yamato. Some Fundamental Properties of Multiple-Valued Kleenean Functions and Determination of Their Logic Formulas
962 -- 967Giuseppe Alia, Enrico Martinelli. On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation
968 -- 980Julio Ortega, Antonio Lloris-Ruíz, Alberto Prieto, Francisco J. Pelayo. Test-Pattern Generation Based on Reed-Muller Coefficients
981 -- 983Judy Stephens, Vijaj Raghavan. On Single-Fault Set Diagnosability in the PMC Model
984 -- 988Anindya Das, Krishnaiyan Thulasiraman, Vinod K. Agarwal, K. B. Lakshmanan. Multiprocessor Fault Diagnosis Under Local Constraints
988 -- 992Sung-Kwong Park, Jung H. Kim. Geometrical Learning Algorithm for Multilayer Neural Networks in a Binary Field
992 -- 997Dinesh P. Mehta, Sartaj Sahni. A Data Structure for Circular String Analysis and Visualization
997 -- 1001John E. Sasinowski, Jay K. Strosnider. A Dynamic Programming Algorithm for Cache/Memory Partitioning for Real-Time Systems
1002 -- 1006Khaled Day, Anand R. Tripathi. Embedding of Cycles in Arrangement Graphs
1007 -- 1009Steven Arno, Ferrell S. Wheeler. Signed Digit Representations of Minimal Hamming Weight
1010 -- 1015Hannes Brunner, Andreas Curiger, Max Hofstetter. On Computing Multiplicative Inverses in GF(2^m)
1015 -- 1020Sarit Mukherjee, Satish K. Tripathi, Dipak Ghosal. A Multiclass Priority-Based Slotted-Ring LAN and Its Analysis
1020 -- 1024T. R. N. Rao, Gui Liang Feng, Mahadev S. Kolluru, Jien-Chung Lo. Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning

Volume 42, Issue 7

769 -- 779Kishore Kota, Joseph R. Cavallaro. Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors
780 -- 793Ramesh K. Sitaraman, Niraj K. Jha. Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems
794 -- 808Abhijit Chatterjee, Manuel A. d Abreu. The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques
809 -- 816Kurt Geihs, Reinhard Heite, Ulf Hollberg. Protected Object References in Heterogeneous Distributed Systems
817 -- 824Jean Duprat, Yvan Herreros, Sylvanus Kla. New Redundant Representations of Complex Numbers and Vectors
825 -- 839Stamatis Vassiliadis, James Phillips, Bart Blaner. Interlock Collapsing ALU s
840 -- 853Hari Krishna, Jenn-Dong Sun. On Theory and Fast Algorithms for Error Correction in Residue Number System Product Codes
854 -- 862Edwin Hsing-Mean Sha, Kenneth Steiglitz. Reconfigurability and Reliability of Systolic/Wavefront Arrays
863 -- 871Woei Lin. Manipulating General Vectors on Synchronous Binary N-Cube
872 -- 881Charles H. Stapper. Improved Yield Models for Fault-Tolerant Memory Chips
882 -- 886Sunggu Lee, Kang G. Shin. Optimal and Efficient Probabilistic Distributed Diagnosis Schemes
887 -- 891Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan. Design of Pseudoexhaustive Testable PLA with Low Overhead
892 -- 896Jien-Chung Lo, Suchai Thanawastien, T. R. N. Rao. Berger Check Prediction for Array Multipliers and Array Dividers

Volume 42, Issue 6

643 -- 650Janusz Rajski, Jerzy Tyszer. Accumulator-Based Compaction of Test Responses
651 -- 664Edward K. Lee, Randy H. Katz. The Performance of Parity Placements in Disk Arrays
665 -- 677Nabanita Das, Bhargab B. Bhattacharya, Jayasree Dattagupta. Isomorphism of Conflict Graphs in Multistage Interconnection Networks and Its Application to Optimal Routing
678 -- 692Russ Miller, Viktor K. Prasanna, Dionisios I. Reisis, Quentin F. Stout. Parallel Computations on Reconfigurable Meshes
693 -- 699Stephen E. Eldridge, Colin D. Walter. Hardware Implementation of Montgomery s Modular Multiplication Algorithm
700 -- 712Stanislaw J. Piestrak. The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks
713 -- 723Yung-Yuan Chen, Shambhu J. Upadhyaya. Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy
724 -- 734Israel Koren, Zahava Koren, Charles H. Stapper. A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits
735 -- 737Reuven Cohen. One-Bit Delay in Ring Networks
737 -- 738Ahmed E. Kamal, V. Carl Hamacher. Response to One-Bit Delay in Ring Networks
738 -- 742David Fernández-Baca, A. Medepalli. Parametric Module Allocation on Partial k-Trees
742 -- 746Alireza Kavianpour, Nader Bagherzadeh. A Systematic Approch for Mapping Application Tasks in Hypercubes
746 -- 752Hussein M. Alnuweiri. A New Class of Optimal Bounded-Degree VLSI Sorting Networks
752 -- 756Richard Hughey. Concurrent Error Detection on Programmable Systolic Arrays
756 -- 759Sidney W. Graham, Steven R. Seidel. The Cost of Broadcasting on Star Graphs and k-Ary Hypercubes
759 -- 764Vitit Kantabutra. Designing Optimum One-Level Carry-Skip Adders
764 -- 768Vijay V. Raghavan. On Asymmetric Invalidation with Partial Tests

Volume 42, Issue 5

513 -- 517Simon Y. Berkovich. An Overlaying Technique for Solving Linear Equations in Real-Time Computing
518 -- 528Douglas M. Blough, Andrzej Pelc. A Clustered Failure Model for the Memory Array Reconfiguration Problem
529 -- 546Jesse Zhixi Fang, Mi Lu. An Iteration Partition Approach for Cache or Local Memory Thrashing on Parallel Processing
547 -- 552Yuichi Saitoh, Hideki Imai. Some Codes for Correcting and Detecting Unidirectional Byte Errors
553 -- 558Hirotsugu Kakugawa, Satoshi Fujita, Masafumi Yamashita, Tadashi Ae. Availability of k-Coterie
559 -- 567Barry G. Douglass. Rearrangeable Three-Stage Interconnection Networks and Their Routing Properties
568 -- 576Daniel Brand, Tsutomu Sasao. Minimization of AND-EXOR Expressions Using Rewrite Rules
577 -- 590Chunming Qiao, Rami G. Melhem. Time-Division Optical Communications in Multiprocessor Arrays
591 -- 596Pablo P. Trabado, Antonio Lloris-Ruíz, Julio Ortega. Solution of Switching Equations Based on a Tabular Algebra
597 -- 607Andrew Lim, Siu-Wing Cheng, Sartaj Sahni. Optimal Joining of Compacted Cells
608 -- 61Giovanni Dimauro, Sebastiano Impedovo, Giuseppe Pirlo. A New Technique for Fast Number Comparison in the Residue Number System
612 -- 616Ding-Zhu Du, Yuh-Dauh Lyuu, D. Frank Hsu. Line Digraph Iterations and Connectivity Analysis of de Bruijn and Kautz Graphs
616 -- 624David T. Harper III, Yashodara Costa. Analytical Estimation of Vector Access Performance in Parallel Memory Architectures
624 -- 630Seshu V. R. Madabhushi, S. Lakshmivarahan, Sudarshan K. Dhall. A Note on Orthogonal Graphs
630 -- 635Daniel J. Rosenkrantz, S. S. Ravi. Improved Bounds for Algorithm-Based Fault Tolerance
636 -- 640Tao Wang, Xinhua Zhuang, Xiaoliang Xing, Xipeng Xiao. A Neuron-Weighted Learning Algorithm and Its Hardware Implementation in Associative Memories

Volume 42, Issue 4

385 -- 395Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath. A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models
396 -- 412Chris H. Perleberg, Alan Jay Smith. Branch Target Buffer Design and Optimization
413 -- 426Marcel Lapointe, Huu Tue Huynh, Paul Fortier. Systematic Design of Pipelined Recursive Filters
427 -- 432Elio D. Di Claudio, Gianni Orlandi, Francesco Piazza. A Systolic Redundant Residue Arithmetic Error Correction Circuit
433 -- 446G. Robert Redinbo, Leonard M. Napolitano Jr., David D. Andaleon. Multibit Correcting Data Interface for Fault-Tolerant Systems
447 -- 457Nageswara S. V. Rao. Computational Complexity Issues in Operative Diagnosis of Graph-Based Systems
458 -- 470. Design and Analysis of Cache Coherent Multistage Interconnection Networks
471 -- 483Ram Raghavan, John P. Hayes. Reducing Inerference Among Vector Accesses in Interleaved Memories
484 -- 493Shambhu J. Upadhyaya, Hoang Pham. Analysis of Noncoherent Systems and an Architecture for the Computation of the System Reliability
494 -- 497Benjamin Arazi. Architectures for Exponentiation Over GF(2^n) Adopted for Smartcard Application
497 -- 501Nobuo Funabiki, Yoshiyasu Takefuji, Kuo Chun Lee. Comparisons of Seven Neural Network Models on Traffic Control Problems in Multistage Interconnection Networks
501 -- 507Shyi-Chyi Cheng, Wen-Hsiang Tsai. A Neural Network Implementation of the Moment-Preserving Technique and Its Application to Thresholding
508 -- 512Jacob van den Berg, Donald F. Towsley. Properties of the Miss Ratio for a 2-Level Storage Model with LRU or FIFO Replacement Strategy and Independent References

Volume 42, Issue 3

257 -- 267Andreas Farid Pour, Mark D. Hill. Performance Implications of Tolerating Cache Faults
268 -- 271Antonio Lioy. On the Equivalence of Fanout-Point Faults
272 -- 280Nageswara S. V. Rao. Expected-Value Analysis of Two Single Fault Diagnosis Algorithms
281 -- 290Jordan L. Holt, Jenq-Neng Hwang. Finite Precision Error Analysis of Neural Network Hardware Implementations
291 -- 299Ananth Sankar, Richard J. Mammone. Growing and Pruning Neural Tree Networks
300 -- 311Martin Lades, Jan C. Vorbrüggen, Joachim M. Buhmann, Jörg Lange, Christoph von der Malsburg, Rolf P. Würtz, Wolfgang Konen. Distortion Invariant Object Recognition in the Dynamic Link Architecture
312 -- 326Krishna R. Pattipati, Yong Li, Henk A. P. Blom. A Unified Framework for the Performability Evaluation of Fault-Tolerant Computer Systems
327 -- 339Meera Balakrishnan, C. S. Raghavendra. An Analysis of a Reliability Model for Repairable Fault-Tolerant Systems
340 -- 352Aloke K. Das, Parimal Pal Chaudhuri. Vector Space Theoretic Analysis of Additive Cellular Automata and Its Application for Pseudoexhaustive Test Pattern Generation
353 -- 358H. Braun, F. C. Stephan. On Optimizing Diameter and Average Distance of Directed Interconnected Networks
358 -- 362Appie van de Liefvoort, Narayan Subramanian. A New Approach for the Performance Analysis of a Single-Bus Multiprocessor System with General Service Times
363 -- 371Antonio M. Gonzalez, José M. Llabería. Reducing Branch Delay to Zero in Pipelined Processors
371 -- 375George Miel. Constant Geometry Fast Fourier Transforms on Array Processors
376 -- 378Colin D. Walter. Systolic Modular Multiplication
379 -- 384Behrooz Parhami. On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems

Volume 42, Issue 2

129 -- 137Sreejit Chakravarty. A Characterization of Binary Decision Diagrams
138 -- 150Imrich Chlamtac, Aura Ganz, Martin G. Kienzle. An HIPPI Interconnection System
151 -- 167Biswanath Mukherjee, Subrata Banerjee. Alternative Strategies for Improving the Fairness in and an Analytical Model of the DQDB Network
168 -- 178Jean Duprat, Jean-Michel Muller. The CORDIC Algorithm: New Results for Fast VLSI Implementation
179 -- 189Niraj K. Jha. Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers
190 -- 204Andrew Choi, Manfred Ruschitzka. Managing Locality Sets: The Model and Fixed-Size Buffers
205 -- 217Douglas M. Blough, Andrzej Pelc. Diagnosis and Repair in Multiprocessor Systems
218 -- 227K. T. Sun, H.-C. Fu. A Hybrid Neural Network Model for Solving Optimization Problems
228 -- 234Tiko Kameda, Slawomir Pilarski, André Ivanov. Notes on Multiple Input Signature Analysis
235 -- 239Raymond E. Fowkes. Hardware Efficient Algorithms for Trigonometric Functions
239 -- 246Paolo Montuschi, Luigi Ciminiera. Reducing Iteration Time When Result Digit is Zero for Radix 2 SRT Division and Square Root with Redundant Remainders
246 -- 253Nian-Feng Tzeng. A Cube-Connected Cycles Architecture with High Reliability and Improved Performance
253 -- 256Anindo Bagchi, S. Louis Hakimi, Edward F. Schmeichel. Gossigping in a Distributed Network

Volume 42, Issue 12

1411 -- 1424Qing Yang. Introducing a New Cache Design into Vector Computers
1425 -- 1439Kien A. Hua, Jeffrey X. W. Su. Dynamic Load Balancing in Very Large Shared-Nothing Hypercube Database Computers
1440 -- 1452Victor F. Nicola, Marvin K. Nakayama, Philip Heidelberger, Ambuj Goyal. Fast Simulation of Highly Dependable Systems with General Failure and Repair Processes
1453 -- 1468Pinaki Mazumder. Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit
1469 -- 1479Ching Yuh Jan, A. Yavuz Oruç. Fast Self-Routing Permutation Switching on an Asymptotically Minimum Cost Network
1480 -- 1486Robert A. Rowley, Bella Bose. Fault-Tolerant Ring Embedding in de Bruijn Networks
1487 -- 1494Ahmed El-Amawy, Morteza Naraghi-Pour, Manju V. Hegde. Noise Modeling Effects in Redundant Synchronizers
1495 -- 1499Vitit Kantabutra. A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
1500 -- 1504Laura A. Sanchis. Multiple-Way Network Partitioning with Different Cost Functions
1504 -- 1506Rolf Johansson. A Class of (12, 8) Codes for Correcting Single Errors and Detecting Double Errors within a Nibble
1506 -- 1510Keumog Ahn, Sartaj Sahni. NP-Hard Module Rotation Problems
1510 -- 1516Hong Hao, Edward J. McCluskey. Analysis of Gate Oxide Shorts in CMOS Circuits
1517 -- 1521Janusz Rajski, Jerzy Tyszer. Recursive Pseudoexhaustive Test Pattern Generation

Volume 42, Issue 11

1281 -- 1293Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath. Reconfiguring Processor Arrays Using Multiple-Track Models: The 3-Track-1-Spare-Approach
1294 -- 1302Mao Chao Lin. Constant Weight Codes for Correcting Symmetric Errors and Detecting Unidirectional Errors
1303 -- 1324Luiz A. Laranjeira, Miroslaw Malek, Roy M. Jenevein. Nest: A Nested-Predicate Scheme for Fault Tolerance
1325 -- 1342Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli. Two-Level Minimization of Multivalued Functions with Large Offsets
1343 -- 1360Giovanni Chiola, Claude Dutheillet, Giuliana Franceschinis, Serge Haddad. Stochastic Well-Formed Colored Nets and Symmetric Modeling Applications
1361 -- 1371Todd P. Kelsey, Kewal K. Saluja, Soo-Young Lee. An Efficient Algorithm for Sequential Circuit Test Generation
1372 -- 1381Kent D. Wilken. An Optimal Graph-Construction Approach to Placing Program Signatures for Signature Monitoring
1382 -- 1388David Hung-Chang Du, Ichiang Lin, K. C. Chang. On Wafer-Packing Problems
1389 -- 1393Vitit Kantabutra. Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
1393 -- 1398Jenn-Yang Tien, Ching-Tien Ho, Wei-Pang Yang. Broadcasting on Incomplete Hypercubes
1398 -- 1403Nader Bagherzadeh, Nayla Nassif, Shahram Latifi. A Routing and Broadcasting Scheme on Faulty Star Graphs
1403 -- 1408Jung Hwan Kim, Phill K. Rhee. The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays

Volume 42, Issue 10

1154 -- 1162Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu. A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
1163 -- 1170Akhilesh Tyagi. A Reduced-Area Scheme for Carry-Select Adders
1171 -- 1183Sang-Hwa Chung, Dan I. Moldovan, Ronald F. DeMara. A Parallel Computational Model for Integrated Speech and Natural Language Understanding
1184 -- 1194Phillip F. Chimento Jr., Kishor S. Trivedi. The Completion Time of Programs on Processors Subject to Failure and Repair
1195 -- 1206Nitin H. Vaidya, Dhiraj K. Pradhan. Fault-Tolerant Design Strategies for High Reliability and Safety
1207 -- 1221Charles J. Colbourn, John S. Devitt, Daryl D. Harms, Miro Kraetzl. Assessing Reliability of Multistage Interconnection Networks
1222 -- 1233Avijit Saha, Chuan-lin Wu, Dun-Sung Tang. Approximation, Dimension Reduction, and Nonconvex Optimization Using Linear Superpositions of Gaussians
1234 -- 1246Eric M. Schwarz, Michael J. Flynn. Parallel High-Radix Nonrestoring Division
1247 -- 1252Nian-Feng Tzeng, Po-Jen Chuang, Chwan-Hwa John Wu. Creating Disjoint Paths in Gamma Interconnection Networks
1253 -- 1256Philip J. Bernhard. Bounds on the Performance of Message Routing Heuristics
1257 -- 1261Thanos Stouraitis. Borrow: A Fault-Tolerance Scheme for Wavefront Array Processors
1261 -- 1266Sulaiman Al-Bassam, Bella Bose. Design of Efficient Error-Correcting Balanced Codes
1267 -- 1271Irith Pomeranz, Sudhakar M. Reddy. Testing of Fault-Tolerant Hardware Through Partial Control of Inputs
1271 -- 1278Shirish Bhide, Nigel M. John, Mansur R. Kabuka. A Boolean Neural Network Approach for the Traveling Salesman Problem
1278 -- 1280M. Anwarul Hasan, Muzhong Wang, Vijay K. Bhargava. A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields

Volume 42, Issue 1

1 -- 14Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan. Modeling Live and Dead Lines in Cache Memory Systems
15 -- 26Huai-An Lin, Chao-Li Tarng. An Inproved Method for Constructing Multiphase Communications Protocols
27 -- 33Shahram Latifi. Combinatorial Analysis of the Fault-Diameter of the n-cube
34 -- 44Gurindar S. Sohi. High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study
45 -- 61Christos A. Papachristou, Venkata R. Immaneni. Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing
62 -- 75Dong Tang, Ravishankar K. Iyer. Dependability Measurement and Modeling of a Multicomputer System
76 -- 82Fernand Boéri, Michel Auguin. OPSILA: A Vector and Parallel Processor
83 -- 98Alexander Thomasian, Victor F. Nicola. Performance Evaluation of a Threshold Policy for Scheduling Readers and Writers
99 -- 102Yu Hen Hu, S. Naganathan. An Angle Recoding Method for CORDIC Algorithm Implementation
102 -- 106David M. Mandelbaum. Some Results on a SRT Type Division Scheme
106 -- 109Tai-Haur Kuo, Hung Chang Lin, Robert C. Potter, Dave Schupe. Multiple-Valued Counter
109 -- 112T. Aaron Gulliver, Vijay K. Bhargava. A Systematic (16, 8) Code for Correcting Double Errors and Detecting Triple-Adjacent Errors
113 -- 118Andrew Spray, Simon Jones. Performance Tradeoffs in Rings of Data-Driven Elements
118 -- 122Christophe Mazenc, Xavier Merrheim, Jean-Michel Muller. Computing Functions cos^{-1} and sin^{-1} Using Cordic
122 -- 127Hwa C. Torng, Martin Day. Interrupt Handling for Out-of-Order Execution Processors