Journal: IEEE Trans. on Circuits and Systems

Volume 56-II, Issue 9

689 -- 693Domenico Pepe, Domenico Zito. 1dB UWB CMOS LNA
694 -- 698Fu-Chuang Chen, Chih-Lung Hsieh. Modeling Harmonic Distortions Caused by Nonlinear Op-Amp DC Gain for Switched-Capacitor Sigma-Delta Modulators
699 -- 703Huy-Hieu Nguyen, Hoai-Nam Nguyen, Jeong-Seon Lee, Sang-Gug Lee. A Binary-Weighted Switching and Reconfiguration-Based Programmable Gain Amplifier
704 -- 708Randall White, Susan Luschas, Shoba Krishnan. Analysis of Errors in a Comparator-Based Switched-Capacitor Biquad Filter
709 -- 713Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai. A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems
714 -- 718Wangren Xu, Zhenying Luo, Sameer R. Sonkusale. Fully Digital BPSK Demodulator and Multilevel LSK Back Telemetry for Biomedical Implant Transceivers
719 -- 723Dong Han, Yuanjin Zheng. A Mixed-Signal GFSK Demodulator Based on Multithreshold Linear Phase Quantization
724 -- 728Jin Sha, Jun Lin, Zhongfeng Wang, Li Li 0003, Minglun Gao. Decoder Design for RS-Based LDPC Codes
729 -- 733Jianwei Zhang, Ming-Yan Yu, Bin-Da Liu, Xiao-Feng Huang. A High-Speed and EDP-Efficient Range-Matching Scheme for Packet Classification
734 -- 738Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou. Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network
739 -- 743Jinhui Zhang, Yuanqing Xia. infty Filter Designs
744 -- 748Jin Zhou, Quanjun Wu. Exponential Stability of Impulsive Delayed Linear Differential Equations

Volume 56-II, Issue 8

613 -- 0Anthony Chan Carusone, Un-Ku Moon. Introducing Jump-Start Tutorials
614 -- 618Dongwon Kwon, Gabriel A. Rincón-Mora. Single-Inductor-Multiple-Output Switching DC-DC Converters
619 -- 623Kamal El-Sankary, Hamed Hanafi Alamdari, Ezz I. El-Masry. An Adaptive ELD Compensation Technique Using a Predictive Comparator
624 -- 628Jean-François Bousquet, Sebastian Magierowski, Geoffrey G. Messier. An Integrated Active Reflector for Phase-Sweep Cooperative Diversity
629 -- 633Francisco Colodro Ruiz, Antonio Jesús Torralba Silgado, Jose Luis Mora, Juana Maria Martinez-Heredia. An Analog Squaring Technique Based on Asynchronous Sigma-Delta Modulation
634 -- 638Cheng C. Wang, Dejan Markovic. Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction
639 -- 643Noha Younis, Mahmoud Ashour, Amin Nassar. Power-Efficient Clock/Data Distribution Technique for Polyphase Comb Filter in Digital Receivers
644 -- 648Katsuki Kobayashi, Naofumi Takagi. m Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions
649 -- 653Young-Won Kim, Joo-Seong Kim, Jae-Hyuk Oh, Yoon-Suk Park, Jong Woo Kim, Kwang-Il Park, Bai-Sun Kong, Young-Hyun Jun. Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation
654 -- 658Zhan-Li Sun. An Extension of MISEP for Post-Nonlinear-Linear Mixture Separation
659 -- 663Shen-Ping Xiao, Xian-Ming Zhang. New Globally Asymptotic Stability Criteria for Delayed Cellular Neural Networks
664 -- 668Guofeng Zhang, Wei Xing Zheng. Stability and Bifurcation Analysis of a Class of Networked Dynamical Systems
669 -- 673Wei Zhou, Jacek M. Zurada. Discrete-Time Recurrent Neural Networks With Complex-Valued Linear Threshold Neurons
674 -- 678Antonio Loría. A Linear Time-Varying Controller for Synchronization of LÜ Chaotic Systems With One Input
679 -- 683Zhisheng Duan, Guanrong Chen. Global Robust Stability and Synchronization of Networks With Lorenz-Type Nodes
684 -- 686Hao Chen. CRT-Based High-Speed Parallel Architecture for Long BCH Encoding

Volume 56-II, Issue 7

525 -- 529Chao-Ching Hung, Shen-Iuan Liu. A Leakage-Compensated PLL in 65-nm CMOS Technology
530 -- 534Martin Anderson, Lars Sundström. DT Modeling of Clock Phase-Noise Effects in LP CT DeltaSigma ADCs With RZ Feedback
535 -- 539Mohammad A. Al-Shyoukh, Hoi Lee. A Compact Ramp-Based Soft-Start Circuit for Voltage Regulators
540 -- 544Lei Zhang, Zhiping Yu, Xiangqing He. Design and Implementation of Ultralow Current-Mode Amplifier for Biosensor Applications
545 -- 549I.-Hsin Wang, Hwei-Yu Lee, Shen-Iuan Liu. An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter
550 -- 554Rui Yu, Yong Ping Xu. Electromechanical-Filter-Based Bandpass Sigma-Delta Modulator
555 -- 559I-Ting Lee, Kun-Hung Tsai, Shen-Iuan Liu. A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider
560 -- 564Yong-Joon Jeon, Young-Suk Son, Jinyong Jeon, Gyu-Hyeong Cho. Improved Transient Current Feedforward Output Buffer for Fast and Compact Active-Matrix OLED Column Drivers
565 -- 569I. Faik Baskaya, David V. Anderson, Sung Kyu Lim. Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing
570 -- 574Mohamed El-Nozahi, Edgar Sánchez-Sinencio, Kamran Entesari. Power-Aware Multiband-Multistandard CMOS Receiver System-Level Budgeting
575 -- 579Alfonso Chacon-Rodriguez, Franco Martin-Pirchio, Silvana Sanudo, Pedro Julián. A Low-Power Integrated Circuit for Interaural Time Delay Estimation Without Delay Lines
580 -- 584Shiyan Hu, Zhuo Li, Charles J. Alpert. A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment
585 -- 589Renatas Jakushokas, Eby G. Friedman. Inductance Model of Interdigitated Power and Ground Distribution Networks
590 -- 594Thibault Hilaire. 2-Dynamic-Range-Scaling Constraints
595 -- 599Hao Liu, I. Mohammed, Yanli Fan, Mark Morgan, Jin Liu. An HDMI Cable Equalizer With Self-Generated Energy Ratio Adaptation Scheme
600 -- 604Xingwen Liu, Wensheng Yu, Long Wang. Stability Analysis of Positive Systems With Bounded Time-Varying Delays
605 -- 609Chengde Zheng, Huaguang Zhang, Zhanshan Wang. Delay-Dependent Globally Exponential Stability Criteria for Static Neural Networks: An LMI Approach

Volume 56-II, Issue 6

429 -- 433Jerry C. Wu, Mona E. Zaghloul. Robust CMOS Micromachined Inductors With Structure Supports for Gilbert Mixer Matching Circuits
434 -- 438Mark S. Oude Alink, André B. J. Kokkeler, Eric A. M. Klumperink, Kenneth C. Rovers, Gerard J. M. Smit, Bram Nauta. Spurious-Free Dynamic Range of a Uniform Quantizer
439 -- 443Frédéric Broydé, Evelyne Clavelier. Signal and Noise Analysis of an MIMO-SSFA
444 -- 448Marvin Onabajo, José Silva-Martínez, Félix O. Fernandez-Rodriguez, Edgar Sánchez-Sinencio. An On-Chip Loopback Block for RF Transceiver Built-In Test
449 -- 453Jaeha Kim. On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs
454 -- 458Saihua Lin, Dawei Huang, Simon Wong. Pi Coil: A New Element for Bandwidth Extension
459 -- 463Francesco Centurelli, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti. Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies
464 -- 468Guansheng Li, Yahya M. Tousi, Arjang Hassibi, Ehsan Afshari. Delay-Line-Based Analog-to-Digital Converters
469 -- 473Bo Yuan, Zhongfeng Wang, Li Li 0003, Minglun Gao, Jin Sha, Chuan Zhang. Area-efficient reed-solomon decoder design for optical communications
474 -- 478Amit Golander, Shlomo Weiss, Ronny Ronen. Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture
479 -- 483Yen-Jen Chang. A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup
484 -- 488Chris Winstead, Sheryl L. Howard. A Probabilistic LDPC-Coded Fault Compensation Technique for Reliable Nanoscale Computing
489 -- 493Aryan Saadat Mehr. Alias-Component Matrices of Multirate Systems
494 -- 498Yong Xiang, Sze-Kui Ng. An Approach to Nonirreducible MIMO FIR Channel Equalization
499 -- 503Zhongyang Fei, Huijun Gao, Wei Xing Zheng. New Synchronization Stability of Complex Networks With an Interval Time-Varying Coupling Delay
504 -- 508Deyi Li, Kun Liu, Yan Sun, MingChang Han. Emerging Clapping Synchronization From a Complex Multiagent Network With Local Information via Local Control
509 -- 513Calin Vladeanu, Safwan El Assad, Jean-Claude Carlach, Raymond Quéré. Improved Frey Chaotic Digital Encoder for Trellis-Coded Modulation
514 -- 518Junchan Zhao, Junan Lu, Qunjiao Zhang. Pinning a Complex Delayed Dynamical Network to a Homogenous Trajectory
519 -- 520Mohammad Saleh Tavazoei. Comments on "Stability Analysis of a Class of Nonlinear Fractional-Order Systems"
519 -- 0Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu. Comments on "A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology"

Volume 56-II, Issue 5

337 -- 338Lucien J. Breems, Peter R. Kinget, K. P. Pun. Special Issue on Circuits and Systems Solutions for Nanoscale CMOS Design Challenges
339 -- 343Yu-lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng. Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique
344 -- 348John A. McNeill, Christopher L. David, Michael C. W. Coln, Rosa Croughwell. "Split ADC" Calibration for All-Digital Correction of Time-Interleaved ADC Errors
349 -- 353Tajeshwar Singh, Trond Sæther, Trond Ytterdal. Feedback Biasing in Nanoscale CMOS Technologies
354 -- 358Shih-An Yu, Peter R. Kinget. Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance
359 -- 363Shih-Hung Chen, Ming-Dou Ker. Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
364 -- 368Timmy Sundström, Atila Alvandpour. Utilizing Process Variations for Reference Generation in a Flash ADC
369 -- 373Mu-Chen Huang, Shen-Iuan Liu. A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator
374 -- 378Armin Tajalli, Yusuf Leblebici. Leakage Current Reduction Using Subthreshold Source-Coupled Logic
379 -- 383Yiming Li, Chih-Hong Hwang, Tien-Yeh Li. Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit
384 -- 388Hamidreza Rezaee-Dehsorkh, Nassim Ravanshad, Reza Lotfi, Khalil Mafinezhad. Modified Model for Settling Behavior of Operational Amplifiers in Nanoscale CMOS
389 -- 393Kadaba Lakshmikumar. Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions
394 -- 398Jyu-Yuan Lai, Chih-Tsun Huang. A Highly Efficient Cipher Processor for Dual-Field Elliptic Curve Cryptography
399 -- 403Tae Ho Im, Insoo Park, Jinmin Kim, Joo-Hyun Yi, Jaekwon Kim, Sungwook Yu, Yong Soo Cho. A New Signal Detection Method for Spatially Multiplexed MIMO Systems and Its VLSI Implementation
404 -- 408Shiann-Rong Kuang, Jiun-Ping Wang, Cang-Yuan Guo. Modified Booth Multipliers With a Regular Partial Product Array
409 -- 413Alfonso Fernández-Vázquez, Gordana Jovanovic-Dolecek. A General Method to Design GCF Compensation Filter
414 -- 418Xingwen Liu. Stability Analysis of Switched Positive Systems: A Switched Linear Copositive Lyapunov Function Method
419 -- 423Jaehoon Song, Juhee Han, Hyunbean Yi, Taejin Jung, Sungju Park. Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults

Volume 56-II, Issue 4

265 -- 269Kyung-Hoon Lim, Gunhyun Ahn, Sung-Chan Jung, Hyun-Chul Park, Min-Su Kim, Ju-Ho Van, Hanjin Cho, Jong-Hyuk Jeong, Cheon-Seok Park, Youngoo Yang. A 60-W Multicarrier WCDMA Power Amplifier Using an RF Predistorter
270 -- 274Chia-Yu Yao, Chih-Chun Hsieh. Hardware Simplification to the Delta Path in a MASH 111 Delta-Sigma Modulator
275 -- 279Baoyong Chi, Jinke Yao, Patrick Chiang, Zhihua Wang. A Fast-Settling Wideband-IF ASK Baseband Circuit for a Wireless Endoscope Capsule
280 -- 284Manuel Carrasco-Robles, Luis Serrano. A Novel Minimum-Size Activation Function and Its Derivative
285 -- 289Amit Acharyya, Koushik Maharatna, Bashir M. Al-Hashimi, Steve R. Gunn. Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry
290 -- 294Guangming Shi, Weifeng Liu, Li Zhang, Fu Li. An Efficient Folded Architecture for Lifting-Based Discrete Wavelet Transform
295 -- 299Vineet Agarwal, Jin Sun, Janet Meiling Wang. Delay Uncertainty Reduction by Gate Splitting
300 -- 304Timothy M. Hollis. Data Bus Inversion in High-Speed Memory Applications
305 -- 309King Hann Lim, Kah Phooi Seng, Li-minn Ang, Siew Wen Chin. Lyapunov Theory-Based Multilayered Neural Network
310 -- 314Liang Chen, Junan Lu, Chi Kong Tse. Synchronization: An Obstacle to Identification of Network Topology
315 -- 319Heinz Koeppl. A Local Nonlinear Model for the Approximation and Identification of a Class of Systems
320 -- 324Chuan-Ke Zhang, Yong He, Min Wu 0002. Improved Global Asymptotical Synchronization of Chaotic Lur'e Systems With Sampled-Data Control
325 -- 329Shengyuan Xu, Wei Xing Zheng, Yun Zou. Passivity Analysis of Neural Networks With Time-Varying Delays
330 -- 334Daesik Park, Chester Sungchung Park, Kwyro Lee. Simple Design of Detector in the Presence of Frequency Offset for IEEE 802.15.4 LR-WPANs

Volume 56-II, Issue 3

185 -- 189Kambiz K. Moez, Mohamed I. Elmasry. A New Loss Compensation Technique for CMOS Distributed Amplifiers
190 -- 194Paul T. M. van Zeijl, Manel Collados. On the Attenuation of DAC Aliases Through Multiphase Clocking
195 -- 199Fredrik Jonsson, Håkan Olsson. A Low-Leakage Open-Loop Frequency Synthesizer Allowing Small-Area On-Chip Loop Filter
200 -- 204Shengxi Diao, Yuanjin Zheng, Chun-Huat Heng. A CMOS Ultra Low-Power and Highly Efficient UWB-IR Transmitter for WPAN Applications
205 -- 209Jaeha Kim. Adaptive-Bandwidth Phase-Locked Loop With Continuous Background Frequency Calibration
210 -- 214Kyoung-Sik Seol, Young-Jin Woo, Gyu-Hyeong Cho, Gyu-Ha Cho, Jae-Woo Lee. A Synchronous Multioutput Step-Up/Down DC-DC Converter With Return Current Control
215 -- 219Jun Lin, Zhongfeng Wang, Li Li 0003, Jin Sha, Minglun Gao. Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders
220 -- 224Yun-Da Huang, Soo-Chang Pei, Jong-Jy Shyu. WLS Design of Variable Fractional-Delay FIR Filters Using Coefficient Relationship
225 -- 229Xiangjun Li, Xinghuo Yu, Changhong Wang, Bingo Wing-Kuen Ling. Periodic Input Response of a Second-Order Digital Filter With Two's Complement Arithmetic
230 -- 234Jianlong Zou, Xikui Ma, Changqing Du. Asymmetrical Oscillations in Digitally Controlled Power-Factor-Correction Boost Converters
235 -- 239Yingying Wu, Wei Wei, Guoyang Li, Ji Xiang. Pinning Control of Uncertain Complex Networks to a Homogeneous Orbit
240 -- 244Chang-Chun Hua, Peter X. Liu. Convergence Analysis of Teleoperation Systems With Unsymmetric Time-Varying Delays
245 -- 249Zheng Wang, K. T. Chau. Design, Analysis, and Experimentation of Chaotic Permanent Magnet DC Motor Drives for Electric Compaction
250 -- 254Chengde Zheng, Huaguang Zhang, Zhanshan Wang. New Delay-Dependent Global Exponential Stability Criterion for Cellular-Type Neural Networks With Time-Varying Delays
255 -- 259Zehui Mao, Bin Jiang, Peng Shi. Protocol and Fault Detection Design for Nonlinear Networked Control Systems
260 -- 261Tso-Bing Juang, Ming-Yu Tsai, Chin-Chieh Chiu. n + 1 Adder Using Circular Carry Selection" [Sep 08 897-901]

Volume 56-II, Issue 2

93 -- 96Juan Pablo Alegre, Santiago Celma, Belén Calvo, N. Fiebig, S. Halder. SiGe Analog AGC Circuit for an 802.11a WLAN Direct Conversion Receiver
97 -- 101Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu. A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology
102 -- 106Miguel Ángel Gutiérrez de Anda, Arturo Sarmiento-Reyes, Luis Hernández-Martínez, Jacek Piskorowski, Roman Kaszynski. The Reduction of the Duration of the Transient Response in a Class of Continuous-Time LTV Filters
107 -- 111Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, Shen-Iuan Liu. A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier
112 -- 116Zhipeng Ye, Michael Peter Kennedy. Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part II: SQ-DDSM
117 -- 121Xiang Gao, Eric A. M. Klumperink, Paul F. J. Geraedts, Bram Nauta. Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops
122 -- 126Ying Khai Teh, Faisal Mohd-Yasin, Florence Choong, Mamun Bin Ibne Reaz, Albert Victor Kordesch. Design and Analysis of UHF Micropower CMOS DTMOST Rectifiers
127 -- 131Armin Tajalli, Massimo Alioto, Yusuf Leblebici. Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits
132 -- 136Owen Casha, Ivan Grech, Franck Badets, Dominique Morche, Joseph Micallef. Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers
137 -- 141Da-Huei Lee, Tai-Haur Kuo, Kow-Liang Wen. Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method
142 -- 146Wei-Ming Lin, Shen-Iuan Liu, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu. A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology
147 -- 151Gerrit Groenewold. Optimal Ladder Filters
152 -- 156Feng Luo, Dongsheng Ma. An Integrated Switching DC-DC Converter With Dual-Mode Pulse-Train/PWM Control
157 -- 161Jaehoon Jeong, Robert Nevels. Time-Domain Analysis of a Lossy Nonuniform Transmission Line
162 -- 166Paolo Maffezzoni, Dario D'Amore. Compact Electrothermal Macromodeling of Photovoltaic Modules
167 -- 171Behrooz Parhami. Efficient Hamming Weight Comparators for Binary Vectors Based on Accumulative and Up/Down Parallel Counters
172 -- 176Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello. Designing High-Speed Adders in Power-Constrained Environments
177 -- 181Giovanni Russo, Mario di Bernardo. Contraction Theory and Master Stability Function: Linking Two Approaches to Study Synchronization of Complex Networks

Volume 56-II, Issue 12

881 -- 885Pin-en Su, Sudhakar Pamarti. Fractional-N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial
886 -- 890Joey Wilson, Andrew Nelson, Behrouz Farhang-Boroujeny. Parameter Derivation of Type-2 Discrete-Time Phase-Locked Loops Containing Feedback Delays
891 -- 895Man Kay Law, Amine Bermak. A 405-nW CMOS Temperature Sensor Based on Linear MOS Operation
896 -- 900Philip M. Chopp, Anas A. Hamoui. Design Constraints for Image-Reject Frequency-Translating Delta Sigma Modulators
901 -- 905Hyun H. Boo, Sungwon Chung, Joel L. Dawson. Adaptive Predistortion Using a DeltaSigma Modulator for Automatic Inversion of Power Amplifier Nonlinearity
906 -- 910Ali Davoudi, Juri Jatskevich, Patrick L. Chapman. Numerical Dynamic Characterization of Peak Current-Mode-Controlled DC-DC Converters
911 -- 915Noureddine Aouzale, Ahmed Chitnalah, Hicham Jakjoud. Experimental Validation of SPICE Modeling Diffraction Effects in a Pulse-Echo Ultrasonic System
916 -- 920Jinook Song, In-Cheol Park. Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines
921 -- 925Shin-Chi Lai, Sheau-Fang Lei, Chia-Lin Chang, Chen-Chieh Lin, Ching-Hsing Luo. Low Computational Complexity, Low Power, and Low Area Design for the Implementation of Recursive DFT and IDFT Algorithms
926 -- 930Kyung Ki Kim, Haiqing Nan, Ken Choi. Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage
931 -- 935Tso-Bing Juang, Sheng-Hung Chen, Huang-Jia Cheng. A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications
936 -- 940Thibault Hilaire. On the Transfer Function Error of State-Space Filters in Fixed-Point Context
941 -- 945Pavel Zahradnik, Miroslav Vlcek. Equiripple Approximation of Half-Band FIR Filters
946 -- 950Yibin Hong, Yue Yang, Litao Yang, Ganesh Samudra, Chun-Huat Heng, Yee-Chia Yeo. SPICE Behavioral Model of the Tunneling Field-Effect Transistor for Circuit Simulation

Volume 56-II, Issue 11

805 -- 809Xiao-Yong He, Kong-Pang Pun, Peter R. Kinget. A 0.5-V Wideband Amplifier for a 1-MHz CT Complex Delta-Sigma Modulator
810 -- 814Bernhard Goll, Horst Zimmermann. A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V
815 -- 819Guohua Zhou, Jianping Xu. Digital Peak Current Control for Switching DC-DC Converters With Asymmetrical Dual-Edge Modulation
820 -- 824Stefano Vitali, Giampaolo Cimatti, Riccardo Rovatti, Gianluca Setti. Adaptive Time-Interleaved ADC Offset Compensation by Nonwhite Data Chopping
825 -- 829Hyungdong Roh, HyoungJoong Kim, Youngkil Choi, Jeongjin Roh, Yi-Gyeong Kim, Jong-Kee Kwon. A 0.6-V Delta-Sigma Modulator With Subthreshold-Leakage Suppression Switches
830 -- 834Joaquin J. Casanova, Zhen Ning Low, Jenshan Lin. Design and Optimization of a Class-E Amplifier for a Loosely Coupled Planar Wireless Power System
835 -- 839Marco Zanuso, Davide Tasca, Salvatore Levantino, Andrea Donadel, Carlo Samori, Andrea L. Lacaita. Noise Analysis and Minimization in Bang-Bang Digital PLLs
840 -- 844Bupesh Pandita, Kenneth W. Martin. Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities
845 -- 849YiBo Zhao, Jiuchao Feng, Chi Kong Tse. Stability Analysis of Periodic Orbits of Nonautonomous Piecewise-Linear Systems by Mapping Approach
850 -- 854Chi-Nan Chuang, Shen-Iuan Liu. A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop
855 -- 859Li-Han Hung, Tai-Cheng Lee. A Split-Based Digital Background Calibration Technique in Pipelined ADCs
860 -- 864Stefan Mendel, Christian Vogel, Nicola Da Dalt. A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming
865 -- 869Xueqiang Wang, Liyang Pan, Dong Wu, Chaohong Hu, Runde Zhou. nor Flash Memories
870 -- 874Yun-Nan Chang. A Fast Spline Curve Rendering Accelerator Architecture
875 -- 879Min Xu, Krishnaiyan Thulasiraman, Xiao-Dong Hu. Conditional Diagnosability of Matching Composition Networks Under the PMC Model

Volume 56-II, Issue 10

753 -- 757Fu-Chuang Chen, Chun-Chieh Huang. Analytical Settling Noise Models of Single-Loop Sigma-Delta ADCs
758 -- 762Song Guo, Hoi Lee. Single-Capacitor Active-Feedback Compensation for Small-Capacitive-Load Three-Stage Amplifiers
763 -- 767Chi-Hao Wu, Chern-Lin Chen. High-Efficiency Current-Regulated Charge Pump for a White LED Driver
768 -- 772Mo M. Zhang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis. Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver
773 -- 777Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim. A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays
778 -- 782Kuan Zhou, John F. McDonald. Impact of Deep-Trench-Isolation-Sharing Techniques on Ultrahigh-Speed Digital Systems
783 -- 787Jian-Hao Lu, Shen-Iuan Liu. A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology
788 -- 792Chih-Peng Fan, Guo-An Su. Fast Algorithm and Low-Cost Hardware-Sharing Design of Multiple Integer Transforms for VC-1
793 -- 797Shin-Chi Lai, Sheau-Fang Lei, Ching-Hsing Luo. Common Architecture Design of Novel Recursive MDCT and IMDCT Algorithms for Application to AAC, AAC in DRM, and MP3 Codecs
798 -- 802Xian-Ming Zhang, Qing-Long Han. A New Stability Criterion for a Partial Element Equivalent Circuit Model of Neutral Type

Volume 56-II, Issue 1

1 -- 5Metin Sengül. Construction of Lossless Ladder Networks With Simple Lumped Elements Connected Via Commensurate Transmission Lines
6 -- 10Young-Suk Seo, Jang-Woo Lee, Hong-Jung Kim, Changsik Yoo, Jae-Jin Lee, Chun-Seok Jeong. A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology
11 -- 15Joung-Yeal Kim, Young-Hyun Jun, Bai-Sun Kong. CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction
16 -- 20Luis Hernández, Enrique Prefasi, Ernesto Pun, Susanna Patón. A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer
21 -- 25Jabeom Koo, Sunghwa Ok, Chulwoo Kim. A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock
26 -- 30Poki Chen, Ting-Chun Liu. Switching Schemes for Reducing Capacitor Mismatch Sensitivity of Quasi-Passive Cyclic DAC
31 -- 35Xiaojun Ma, Fabrizio Lombardi. On the Computational Complexity of Tile Set Synthesis for DNA Self-Assembly
36 -- 40Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan. Self-Biased Unity-Gain Buffers With Low Gain Error
41 -- 45Antonio Jesús Torralba Silgado, Clara Isabel Lujan-Martinez, Ramón González Carvajal, Juan Antonio Gómez Galán, Melita Pennisi, Jaime Ramírez-Angulo, Antonio J. López-Martín. Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques
46 -- 50Laurent-Stéphane Didier, Pierre-Yves Rivaille. A Generalization of a Fast RNS Conversion for a New 4-Modulus Base
51 -- 55Pei-Yin Chen, Chien-Chuan Huang, Yeu-Horng Shiau, Yao-Tung Chen. A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images
56 -- 60Jaehoon Song, Juhee Han, Hyunbean Yi, Taejin Jung, Sungju Park. Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults
61 -- 65Leena Vachhani, K. Sridharan, Pramod Kumar Meher. Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation
66 -- 70Tiebao Yang, Xiang Chen. Local Robustness of Hopf Bifurcation Stabilization
71 -- 75Guoliang Wei, Zidong Wang, Xiao He, Huisheng Shu. Filtering for Networked Stochastic Time-Delay Systems With Sector Nonlinearity
76 -- 80Francesco Amato, Carlo Cosentino, Antonino S. Fiorillo, Alessio Merola. Stabilization of Bilinear Systems Via Linear State-Feedback Control
81 -- 85Ji-Hoon Kim, In-Cheol Park. Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes
86 -- 90Imtinan Elahi, Khurram Muhammad, Poras T. Balsara. Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation