Chi-Chang Lu - researchr alias

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Viewing Publication 1 - 23 from 23

2020

A High-Precision Bandgap Reference With a V-Curve Correction CircuitChang-Chi Lee, Hou-Ming Chen, Chi-Chang Lu, Bo-Yi Lee, Hsien-Chi Huang, He-Sheng Fu, Yong-Xin Lin. access, 8:62632-62638, 2020. [doi]

A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching SchemeChi-Chang Lu, Ding-Ke Huang. access, 8:28257-28266, 2020. [doi]

2019

1.2 V 10-bits 40 MS/s CMOS SAR ADC for low-power applicationsChi-Chang Lu, Ding-Ke Huang. iet-cds, 13(6):857-862, 2019. [doi]

Capacitive digital-to-analog converter for low-power SAR ADCsChi-Chang Lu, Sheng-Yan Lai. icce-tw 2019: 1-2 [doi]

2018

Intelligent Infant Monitoring System Involving a Wi-Fi Wireless Sensor NetworkChi-Chang Lu, Chung-Hsien Wu, Hui-Kai Su. iih-msp 2019: 269-276 [doi]

2015

A Study of the Accessible Approach to Replace the Reservoir Silt Glaze with New FormulaChi-Chang Lu, Po-Hsien Lin. hci 2015: 83-95 [doi]

2014

Cultural Creativity in Design Strategy: A Case Study of User's Preference of a Bird-Shaped TeapotChi-Chang Lu, Po-Hsien Lin. hci 2014: 775-785 [doi]

2013

A 1.2V 10-bit 5 MS/s CMOS cyclic ADCChi-Chang Lu. iscas 2013: 1986-1989 [doi]

Research on Symbol Expression for Eye Image in Product Design: The Usage of the Chinese Traditional "Yun Wen"Chi-Chang Lu, Po-Hsien Lin. hci 2013: 128-137 [doi]

2011

A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold CircuitTsung-Sum Lee, Chi-Chang Lu. cssp, 30(5):883-898, 2011. [doi]

Design for Aesthetic ExperiencePo-Hsien Lin, Chi-Chang Lu, Mo-Li Yeh. hci 2011: 322-331 [doi]

A Study of Producing Ceramic Glaze Utilizing Shihmen Reservoir SiltChi-Chang Lu, Po-Hsien Lin. hci 2011: 201-210 [doi]

2010

2008

A CMOS low-voltage fully differential sample-and-hold circuitChi-Chang Lu, Wei-Xiang Tung, Chien-Kuo Huang. apccas 2008: 1188-1191 [doi]

2007

A 250MHz 11BIT 20mW low-hold-pedestal CMOS fully differential track-and-hold circuitTsung-Sum Lee, Chi-Chang Lu, Jian-Ting Zhan. socc 2007: 47-50 [doi]

A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital ConverterChi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee. iscas 2007: 1955-1958 [doi]

A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital ConverterChi-Chang Lu, Tsung-Sum Lee. tcas, 54-II(8):658-662, 2007. [doi]

2005

A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestalTsung-Sum Lee, Chi-Chang Lu, Shen-Hau Yu, Jian-Ting Zhan. iscas 2005: 3111-3114 [doi]

A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestalTsung-Sum Lee, Chi-Chang Lu. tcas, 52-I(9):1752-1757, 2005. [doi]

2003

A fully differential low-voltage CMOS high-speed track-and-hold circuitTsung-Sum Lee, Chi-Chang Lu. iscas 2003: 397-400 [doi]

2002

A low-voltage fully differential CMOS high-speed track-and-hold circuitTsung-Sum Lee, Chi-Chang Lu. apccas 2002: 141-144 [doi]

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