Chun-Hua Cheng - researchr alias

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Viewing Publication 1 - 29 from 29

2020

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable WrappersJui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng. vts 2020: 1-6 [doi]

2016

Power-mode-aware buffer synthesis for low-power clock skew minimizationShih-Hsu Huang, Chun-Hua Cheng. ieiceee, 13(14):20160511, 2016. [doi]

2014

Live demonstration: A low-power high-level synthesis systemHua-Hsin Yeh, Chun-Hua Cheng, Shih-Hsu Huang. apccas 2014: 165-166 [doi]

2013

Co-synthesis of data paths and clock control paths for minimum-period clock gatingWen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng. date 2013: 1831-1836 [doi]

2012

Simultaneous wafer bonding type selection and layer assignment for TSV count minimizationChun-Hua Cheng, Wei-Shuo Tzeng, Shih-Hsu Huang. apccas 2012: 627-630 [doi]

Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuitsWen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng. aspdac 2012: 245-250 [doi]

A formal approach to slack-driven high-level synthesisHua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng. iscas 2012: 584-587 [doi]

2011

Teaching three-dimensional system-in-package design automation in a semester courseShih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng. mse 2011: 52-55 [doi]

Accurate TSV Number Minimization in High-Level SynthesisChih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng. jise, 27(5):1527-1543, 2011. [doi]

2010

Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current MinimizationShih-Hsu Huang, Chun-Hua Cheng. jise, 26(6):2249-2266, 2010. [doi]

2009

2008

Module binding for low power clock gatingChun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu. ieiceee, 5(18):762-768, 2008. [doi]

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power ManagementShih-Hsu Huang, Chun-Hua Cheng. ieicet, 91-A(1):375-382, 2008. [doi]

Power-Management Scheduling for Peak Power MinimizationShih-Hsu Huang, Chun-Hua Cheng. jise, 24(6):1647-1668, 2008. [doi]

2007

Clock Period Minimization with Minimum Delay InsertionShih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh. dac 2007: 970-975 [doi]

Operation scheduling for the synthesis of false loop free circuitsShih-Hsu Huang, Chun-Hua Cheng. ieiceee, 4(14):448-454, 2007. [doi]

Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power DifferentialWei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng. euc 2007: 638-647 [doi]

2006

2005

A formal approach to the slack driven scheduling problem in high-level synthesisShih-Hsu Huang, Chun-Hua Cheng. iscas 2005: 5633-5636 [doi]

Three-dimension scheduling under multi-cycle interconnect communicationsShih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng. ieiceee, 2(4):108-114, 2005. [doi]

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