Roberto Suaya - researchr alias

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Viewing Publication 1 - 19 from 19

2019

Low Power SPI Design Based on Relative Timing TechniquesGuillermo H. Makar, Francisco J. Badenas, Roberto G. Simone, Alejandro Furfaro, Kenneth S. Stevens, Roberto Suaya. icecsys 2019: 166-169 [doi]

2013

Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nmShomit Das, Georgios Manetas, Kenneth S. Stevens, Roberto Suaya. nocs 2013: 1-2 [doi]

2012

An efficient framework for passive compact dynamical modeling of multiport linear systemsZohaib Mahmood, Roberto Suaya, Luca Daniel. date 2012: 1203-1208 [doi]

Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple SubstratesChuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee. tcad, 31(11):1698-1710, 2012. [doi]

2010

Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrateNavin Srivastava, Roberto Suaya, Kaustav Banerjee. date 2010: 459-464 [doi]

Corrections to Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate [Jul 09 1047-1060]Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee. tcad, 29(5):849, 2010. [doi]

2009

Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive SubstrateNavin Srivastava, Roberto Suaya, K. Banerjee. tcad, 28(7):1047-1060, 2009. [doi]

2008

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting SubstrateNavin Srivastava, Roberto Suaya, Kaustav Banerjee. date 2008: 426-431 [doi]

2007

Efficient implementation of conduction modes for modelling skin effectSalvador Ortiz, Roberto Suaya. isvlsi 2007: 500-505 [doi]

2006

Mutual inductance between intentional inductors: closed form expressionsRafael Escovar, Salvador Ortiz, Roberto Suaya. iscas 2006: [doi]

Fullwave volumetric Maxwell solver using conduction modesSalvador Ortiz, Roberto Suaya. iccad 2006: 13-18 [doi]

2005

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen. aspdac 2005: [doi]

An improved long distance treatment for mutual inductanceRafael Escovar, Salvador Ortiz, Roberto Suaya. tcad, 24(5):783-793, 2005. [doi]

2004

Optimal design of clock trees for multigigahertz applicationsRafael Escovar, Roberto Suaya. tcad, 23(3):329-345, 2004. [doi]

Mutual inductance extraction and the dipole approximationRafael Escovar, Salvador Ortiz, Roberto Suaya. ispd 2004: 162-169 [doi]

2002

Transmission line design of clock treesRafael Escovar, Roberto Suaya. iccad 2002: 334-340 [doi]

1991

A Two-Dimensional Topological Compactor With Octagonal GeometryPaul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya. dac 1991: 727-731 [doi]

From formal verification to silicon compilationJeffrey Joyce, Erwin Liu, John M. Rushby, Natarajan Shankar, Roberto Suaya, Friedrich W. von Henke. compcon 1991: 450-455 [doi]

1990

Two-dimensional IC layout compaction based on topological design rule checkingJohn Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya. tcad, 9(3):260-275, 1990. [doi]

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