Table of Contents

• Future Developments in Information Technology (abstract)Ian M. Ross. 1 [doi]
• Twenty-Five Years of Electronic Design AutomationA. Richard Newton. 2 [doi]
• An Automated BIST Approach for General Sequential Logic SynthesisCharles E. Stroud. 3-8 [doi]
• Automatic Insertion of BIST Hardware Using VHDLKwanghyun Kim, Joseph G. Tront, Dong Sam Ha. 9-15 [doi]
• VLSI Design Synthesis with TestabilityCatherine H. Gebotys, Mohamed I. Elmasry. 16-21 [doi]
• A Defect-Tolerant and Fully Testable PLANorbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth. 22-33 [doi]
• VHDL: A Call for StandardsDavid R. Coelho. 40-47 [doi]
• Verification of VHDL Designs Using VALLarry M. Augustin, Benoit A. Gennart, Youm Huh, David C. Luckham, Alec G. Stanculescu. 48-53 [doi]
• A Module Area Estimator for VLSI LayoutXinghao Chen, Michael L. Bushnell. 54-59 [doi]
• A New Area and Shape Function Estimation Technique for VLSI LayoutsGerhard Zimmermann. 60-65 [doi]
• Optimal Aspect Ratios of Building Blocks in VLSIShmuel Wimer, Israel Koren, Israel Cederbaum. 66-72 [doi]
• Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated AnnealingCarl Sechen. 73-80 [doi]
• Contest: A Concurrent Test Generator for Sequential CircuitsVishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal. 84-89 [doi]
• A Method of Delay Fault Test GenerationC. Thomas Glover, M. Ray Mercer. 90-95 [doi]
• Split Circuit Model for Test GenerationWu-Tung Cheng. 96-101 [doi]
• A Notation for Describing Multiple Views of VLSI CircuitsJean-Loup Baer, Meei-Chiueh Liem, Larry McMurchie, Rudolf Nottrott, Lawrence Snyder, Wayne Winder. 102-107 [doi]
• A Graphical Hardware Design LanguagePaul J. Drongowski, Jwahar R. Bami, Ranganathan Ramaswamy, Sundar Iyengar, Tsu-Hua Wang. 108-114 [doi]
• A Human Machine Interface for Silicon CompilationGotaro Odawara, Masahiro Tomita, Kazuhiko Hattori, Osamu Okuzawa, Toshiaki Hirata, Masayasu Ochiai. 115-120 [doi]
• Parallel Placement on Reduced Array ArchitectureC. P. Ravi Kumar, Sarma Sastry. 121-127 [doi]
• Parallel Channel RoutingMehdi R. Zargham. 128-133 [doi]
• Mask Verification on the Connection MachineErik C. Carlson, Rob A. Rutenbar. 134-140 [doi]
• On Path Selection in Combinational Logic CircuitsWing Ning Li, Sudhakar M. Reddy, Sartaj Sahni. 142-147 [doi]
• ATV: An Abstract Timing VerifierDavid E. Wallace, Carlo H. Séquin. 154-159 [doi]
• An Empirical Study of On-chip ParallelismMary L. Bailey, Lawrence Snyder. 160-165 [doi]
• Parallel Logic Simulation on General Purpose MachinesLarry Soulé, Tom Blank. 166-171 [doi]
• A Programmable Hardware Accelerator for Compiled Electrical SimulationDavid M. Lewis. 172-177 [doi]
• Multi-Pads, Single Layer Power Net Routing in VLSI CircuitsH. Cai. 183-188 [doi]
• LocusRoute: A Parallel Global Router for Standard CellsJonathan Rose. 189-195 [doi]
• Behavioral Modeling for System Design (panel)Tom Blank. 196 [doi]
• Formal Specification and Verification of Hardware: A Comparative Case StudyVictoria Stavridou, Howard Barringer, David A. Edwards. 197-204 [doi]
• Proving Circuit Correctness Using Formal Comparison Between Expected and Extracted BehaviourJean Christophe Madre, Jean-Paul Billon. 205-210 [doi]
• Formal Verification of the Sobel Image Processing ChipPaliath Narendran, Jonathan Stillman. 211-217 [doi]
• The IBM Engineering Verification EngineDaniel K. Beece, George Deibert, Georgina Papp, Frank Villante. 218-224 [doi]
• Logic Simulation System Using Simulation Processor (SP)Minoru Saitoh, Kenji Iwata, Akiko Nokamura, Makoto Kakegawa, Junichi Masuda, Hirofumi Hamamura, Fumiyasu Hirose, Nobuaki Kawato. 225-230 [doi]
• Algorithm for Vectorizing Logic Simulation and Evaluation of VELVET PerformanceYoshiharu Kazama, Yoshiaki Kinoshita, Motonobu Nagafuji, Hiroshi Murayama. 231-236 [doi]
• A Structural Representation for VLSI DesignRichard Barth, Bertrand Serlet. 237-242 [doi]
• Parameterized SchematicsRichard Barth, Bertrand Serlet, Pradeep S. Sindhu. 243-249 [doi]
• Patchwork: Layout from Schematic AnnotationsRichard Barth, Louis Monier, Bertrand Serlet. 250-255 [doi]
• What Is a Design Automation Framework, Anyway? (panel)Wayne Wolf. 256 [doi]
• A Database Management System for a VLSI Design SystemGwo-Dong Chen, Tai-Ming Parng. 257-262 [doi]
• Browsing in Chip Design DatabaseDavid Gedye, Randy H. Katz. 269-274 [doi]
• Versions and Change Notification in an Object-Oriented Database SystemHong-Tai Chou, Won Kim. 275-281 [doi]
• An Accurate and Efficient Gate Level Delay Calculator for MOS CircuitsFoong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam. 282-287 [doi]
• Delay Modeling and Time of Bipolar Digital CircuitsDaniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj. 288-293 [doi]
• Pattern-Independent Current Estimation for Reliability Analysis of CMOS CircuitsRichard Burch, Farid N. Najm, Ping Yang, Dale E. Hocevar. 294-299 [doi]
• Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of CharacteristicsCarol V. Gura, Jacob A. Abraham. 300-305 [doi]
• Performance of a New Annealing ScheduleJimmy Lam, Jean-Marc Delosme. 306-311 [doi]
• Clustering Based Simulated Annealing for Standard Cell PlacementSivanarayana Mallela, Lov K. Grover. 312-317 [doi]
• Proud: A Fast Sea-of-Gates Placement AlgorithmRen-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu. 318-323 [doi]
• A Quadratic Metric with a Simple Solution Scheme for Initial PlacementLawrence T. Pillage, Ronald A. Rohrer. 324-329 [doi]
• Tutorial on High-Level SynthesisMichael C. McFarland, Alice C. Parker, Raul Camposano. 330-336 [doi]
• The System Architect s WorkbenchDonald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn. 337-343 [doi]
• A Context Mechanism to Control Sharing in a Design DatabaseDenise J. Ecklund, Fred M. Tonge. 344-350 [doi]
• Object Type Oriented Data Modeling for VLSI Data ManagementPieter van der Wolf, T. G. R. van Leuken. 351-356 [doi]
• Concurrency Control in a VLSI Design DatabaseIng Widya, T. G. R. van Leuken, Pieter van der Wolf. 357-362 [doi]
• Automated Design Software for Switched-Capacitor IC s with Symbolic Simulator SCYMBALAgnieszka Konczykowska, M. Bon. 363-368 [doi]
• Analog Compilation Based on Successive DecompositionsE. Berkcan, Manuel A. d Abreu, W. Laughton. 369-375 [doi]
• Model Development and Verification for High Level Analog BlocksChandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen. 376-382 [doi]
• Symbolic Layout Compaction ReviewDavid G. Boyer. 383-389 [doi]
• Compaction with Incremental Over-Constraint ResolutionWerner L. Schiele. 390-395 [doi]
• An Efficient Compactor for 45° LayoutDavid Marple, Michiel Smulders, Henk Hegen. 396-402 [doi]
• MILO: A Microarchitecture and Logic OptimizerNels Vander Zanden, Daniel Gajski. 403-408 [doi]
• BECOME: Behavior Level Circuit Synthesis Based on Structure MappingRuey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou. 409-414 [doi]
• Bridge: A Versatile Behavioral Synthesis SystemChia-Jeng Tseng, Ruey-Sing Wei, Steven G. Rothweiler, Michael M. Tong, Ajoy K. Bose. 415-420 [doi]
• PLAYGROUND: Minimization of PLAs with Mixed Ground True OutputsChin-Long Wey, Tsin-Yuan Chang. 421-426 [doi]
• A Fast Algorithm to Minimize Multi-Output Mixed-Polarity Generalized Reed-Muller FormsMartin Helliwell, Marek A. Perkowski. 427-432 [doi]
• A Kernel-Finding State Assignment Algorithm for Multi-Level LogicWayne Wolf, Kurt Keutzer, Janaki Akella. 433-438 [doi]
• A High Packing Density Module Generator for CMOS Logic CellsYoichi Shiraishi, Jun ya Sakemi, Makoto Kutsuwada, Akira Tsukizoe, Takashi Satoh. 439-444 [doi]
• SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit SchematicsDonald G. Baltus, Jonathan Allen. 445-452 [doi]
• An Electrical Optimizer that Considers Physical LayoutFred W. Obermeier, Randy H. Katz. 453-459 [doi]
• Analyzing CMOS Power Supply Networks Using ArielDon Stark, Mark Horowitz. 460-464 [doi]
• RISCE - A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout VerificationVolker Henkel, Ulrich Golze. 465-470 [doi]
• Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo. 471-475 [doi]
• CAD Tool Needs for System DesignersRandal E. Bryant. 476 [doi]
• High-Level Synthesis: Current Status and Future DirectionsGaetano Borriello, Ewald Detjens. 477-482 [doi]
• HERCULES - a System for High-Level SynthesisGiovanni De Micheli, David C. Ku. 483-488 [doi]
• Design Process Model in the Yorktown Silicon CompilerRaul Camposano. 489-494 [doi]
• Fast Incremental Circuit Analysis Using Extracted HierarchyDerek L. Beatty, Randal E. Bryant. 495-500 [doi]
• Incremental-in-time Algorithm for Digital SimulationKiyoung Choi, Sun Young Hwang, Tom Blank. 501-505 [doi]
• A Circuit Comparison System with Rule-Based Functional Isomorphism CheckingMakoto Takashima, Atsuhiko Ikeuchi, Shoichi Kojima, Toshikazu Tanaka, Tamaki Saitou, Jun-ichi Sakata. 512-516 [doi]
• Will Cell Generation Displace Standard Cells?Alfred E. Dunlop. 528 [doi]
• CORAL II: Linking Behavior and Structure in an IC Design SystemRobert L. Blackburn, Donald E. Thomas, Patti M. Koenig. 529-535 [doi]
• Module Selection for Pipelined SynthesisRajiv Jain, Alice C. Parker, Nohbyung Park. 542-547 [doi]
• The Use of Petri Nets for Modeling Pipelined ProcessorsRami R. Razouk. 548-553 [doi]
• Fast Algorithm for Optimal Layer AssignmentY. S. Kuo, T. C. Chern, Wei Kuan Shih. 554-559 [doi]
• Connectivity Biased Channel Construction and Ordering for Building-Block LayoutH. Cai. 560-565 [doi]
• A New Approach to the Pin Assignment ProblemXianji Yao, Masaaki Yamada, C. L. Liu. 566-572 [doi]
• The Constrained Via Minimization Problem for PCB and VLSI DesignXiao-Ming Xiong, Ernest S. Kuh. 573-578 [doi]
• Micro-operation Perturbations in Chip Level Fault ModelingChien-Hung Chao, F. Gail Gray. 579-582 [doi]
• A New Two Task Algorithm for Clock Mode Fault Simulation in Sequential CircuitsFredrick J. Hill, Eltayeb Abuelyamen, Wei-Kang Huang, Guo-Qiang Shen. 583-586 [doi]
• Dytest: A Self-Learning Algorithm Using Dynamic Testability Measures to Accelerate Test GenerationWeiwei Mao, Michael D. Ciletti. 591-596 [doi]
• CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited TopologyRhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler. 597-600 [doi]
• A Graph Compaction Approach to Fault SimulationDov Harel, Balakrishnan Krishnamurthy. 601-604 [doi]
• Automatic Functional Test Program Generation for MicroprocessorsChen-Shang Lin, Hong-Fa Ho. 605-608 [doi]
• Spare Allocation and Reconfiguration in Large Area VLSISy-Yen Kuo, W. Kent Fuchs. 609-612 [doi]
• The Architecture of a Highly Integrated Simulation SystemMichel Heydemann, Alain Plaignaud, Daniel Dure. 617-621 [doi]
• Constraint Propagation in an Object-Oriented IC Design EnvironmentTai A. Ly, Emil F. Girczyc. 628-633 [doi]
• Automatic Building of Graphs for Rectangular DualisationMarwan A. Jabri. 638-641 [doi]
• Automatic Layout Procedures for Serial Routing DevicesYasushi Ogawa, Hidekazu Terai, Tokinori Kozawa. 642-645 [doi]
• A Digit-Serial Silicon CompilerRichard I. Hartley, Peter F. Corbett. 646-649 [doi]
• DECOMPOSER: A Synthesizer for Systolic SystemsPao-Po Hou, Robert Michael Owens, Mary Jane Irwin. 650-653 [doi]
• SMART: Tools and Methods for Synthesis of VLSI Chips with Processor ArchitectureThomas Bergstraesser, Jürgen Gessner, Karlheinz Hafner, Stefan Wallstab. 654-657 [doi]
• Routing Algorithm for Gate Array Macro CellsAtreyi Chakraverti, Moon-Jung Chung. 658-662 [doi]
• An Interactive Maze Router with HintsMichael H. Arnold, Walter S. Scott. 672-676 [doi]
• Improved Channel Routing by Via Minimization and ShiftingChung-Kuan Cheng, David N. Deutsch. 677-680 [doi]
• The Min-cut Shuffle: Toward a Solution for the Global Effect Problem of Min-cut PlacementInderpal S. Bhandari, Mark Hirsch, Daniel P. Siewiorek. 681-685 [doi]
• Fault Simulation in a Distributed EnvironmentPatrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers. 686-691 [doi]
• The Performance of the Concurrent Fault Simulation Algorithms in MOZARTSilvano Gai, Pier Luca Montessoro, Fabio Somenzi. 692-697 [doi]
• Why Partial Design Verification Works Better Than It ShouldJacob Savir. 704-707 [doi]
• Advances in Functional Abstraction from StructureRichard H. Lathrop, Robert J. Hall, Gavan Duffy, K. Mark Alexander, Robert S. Kirk. 708-711 [doi]
• Hardware Logic Simulation by CompilationCraig Hansen. 712-716 [doi]
• Clock Event Suppression Algorithm of VELVET and Its Application to S-820 DevelopmentYoshio Takamine, Shunsuke Miyamoto, Shigeo Nagashima, Masayuki Miyoshi, Shun Kawabe. 716-719 [doi]
• A Path Selection Algorithm for Timing AnalysisH.-C. Yen, Subbarao Ghanta, David Hung-Chang Du. 720-723 [doi]