Table of Contents

• Plenary presentations: Keynote: The product complexity and test - How product complexity impacts test industryMichael Campbell. 9 [doi]
• Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performanceAbhijit Chatterjee. 10 [doi]
• Adaptive test directionsPeter Maxwell. 12-16 [doi]
• Production test challenges for highly integrated mobile phone SOCs - A case studyFrank Poehl, Frank Demmerle, Juergen Alt, Hermann Obermeir. 17-22 [doi]
• Test-architecture optimization for TSV-based 3D stacked ICsBrandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree. 24-29 [doi]
• A low-cost and scalable test architecture for multi-core chipsChun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li. 30-35 [doi]
• On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stackingJouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis. 36-41 [doi]
• On the use of standard digital ATE for the analysis of RF signalsNicolas Pous, Florence Azaïs, Laurent Latorre, Jochen Rivoir. 43-48 [doi]
• Sensors for built-in alternate RF testLouay Abdallah, Haralampos-G. D. Stratigopoulos, Christophe Kelma, Salvador Mir. 49-54 [doi]
• Low-cost signature test of RF blocks based on envelope response analysisManuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas. 55-60 [doi]
• Combining scan and trace buffers for enhancing real-time observability in post-silicon debuggingHo Fai Ko, Nicola Nicolici. 62-67 [doi]
• Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysisElena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras. 69-74 [doi]
• A low-cost built-in self-test scheme for an array of memoriesYu-Jen Huang, Che-Wei Chou, Jin-Fu Li. 75-80 [doi]
• A two-layer SPICE model of the ATMEL TSTAC:::TM::: eFlash memory technology for defect injection and faulty behavior predictionP.-D. Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, B. Godard, G. Festes, L. Vachez. 81-86 [doi]
• A transient error tolerant self-timed asynchronous architectureMasoud Zamani, Mehdi Baradaran Tahoori. 88-93 [doi]
• Multiple fault diagnosis in crossbar nano-architecturesNavid Farazmand, Mehdi Baradaran Tahoori. 94-99 [doi]
• Full-circuit SPICE simulation based validation of dynamic delay estimationKe Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor. 101-106 [doi]
• On estimation of NBTI-Induced delay degradationMitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura. 107-111 [doi]
• Modified T-Flip-Flop based scan cell for RASRaghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh. 113-118 [doi]
• Calibration-enabled scalable built-in current sensor compatible with very low cost ATESachin Dileep Dasnurkar, Jacob A. Abraham. 119-124 [doi]
• Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICsJose Luis Garcia-Gervacio, Víctor H. Champac. 126-131 [doi]
• Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodesRenan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine. 132-137 [doi]
• A reconfigurable online BIST for combinational hardware using digital neural networksS. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi. 139-144 [doi]
• A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge controlHyunjin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo. 145-150 [doi]
• Constructing augmented time compactorsEmil Gizdarski. 151-156 [doi]
• Predicting dynamic specifications of ADCs with a low-quality digital input signalXiaoqin Sheng, Vincent Kerzerho, Hans G. Kerkhoff. 158-163 [doi]
• Test of embedded analog circuits based on a built-in current sensorRomán Mozuelos, Yolanda Lechuga, Mar Martínez, Salvador Bracho. 164-169 [doi]
• Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applicationsVezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner. 170-174 [doi]
• Improving CNF representations in SAT-based ATPG for industrial circuits using BDDsDaniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler. 176-181 [doi]
• A distributed architecture to check global properties for post-silicon debugErik Larsson, Bart Vermeulen, Kees Goossens. 182-187 [doi]
• Automated conformance evaluation of SystemC designs using timed automataPaula Herber, Marcel Pockrandt, Sabine Glesner. 188-193 [doi]
• A software-based self-test methodology for system peripheralsMichelangelo Grosso, Wilson J. H. Perez, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, J. Velasco Medina. 195-200 [doi]
• Microprocessor fault-tolerance via on-the-fly partial reconfigurationStefano Di Carlo, Andrea Miele, Paolo Prinetto, Antonio Trapanese. 201-206 [doi]
• Scan based speed-path debug for a microprocessorJing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz. 207-212 [doi]
• An integrated flow for the design of hardened circuits on SRAM-based FPGAsCristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante. 214-219 [doi]
• Diagnosis of failing scan cells through orthogonal response compactionBrady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer. 221-226 [doi]
• An adaptive tester architecture for volume diagnosisPaolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda. 227-232 [doi]
• Diagnosis of full open defects in interconnect lines with fan-outRosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman. 233-238 [doi]
• Input test data volume reduction based on test vector chainsIrith Pomeranz, Sudhakar M. Reddy. 240 [doi]
• On measurement uncertainty of ADC nonlinearities in oscillation-based testPeter Mrak, Anton Biasizzo, Franc Novak. 241 [doi]
• Fast simulation based testing of anti-tearing mechanisms for small embedded systemsJohannes Loinig, Christian Steger, Reinhold Weiss, Ernst Haselsteiner. 242 [doi]
• New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access MechanismXiao Zhang, Hans G. Kerkhoff, Bart Vermeulen. 243 [doi]
• Design and implementation of Automatic Test Equipment IP moduleS. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich. 244 [doi]
• Add-on blocks and algorithms for improving stimulus compressionNader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla. 245 [doi]
• Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonizationSezer Gören, H. Fatih Ugurdag, Okan Palaz. 246 [doi]
• Hybrid test application in hybrid delay scan designYuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue. 247 [doi]
• Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraintsSobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu. 248 [doi]
• Test power reduction in compression-based reconfigurable scan architecturesSobeeh Almukhaizim, Mohammad Gh. Mohammad, Mohammad Khajah. 249 [doi]
• Multivariate model for test response analysisShaji Krishnan, Hans G. Kerkhoff. 250 [doi]
• Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGAGaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin. 251 [doi]
• Evaluation of concurrent error detection techniques on the Advanced Encryption StandardK. Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 252 [doi]
• Algorithm-based fault tolerance for many-core architecturesClaus Braun, Hans-Joachim Wunderlich. 253 [doi]
• A diagnostic test generation system and a coverage metricYu Zhang, Vishwani D. Agrawal. 254 [doi]
• A shared BIST optimization methodology for memory testLilia Zaourar, Jihane Alami Chentoufi, Yann Kieffer, Arnaud Wenzel, Frederic Grandvaux. 255 [doi]
• Pipelined parallel test structure for mixed-signal SoCsYang Jin, Hong Wang, Zhengliang Lv, Shiyuan Yang. 256 [doi]
• Setting test conditions for improving SRAM reliabilityRenan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine. 257 [doi]
• Configurable fault-tolerant link for inter-die communication in 3D on-chip networksVladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi. 258 [doi]
• Scan cell reordering to minimize peak power during test cycle: A graph theoretic approachJaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara. 259 [doi]
• Test pattern selection to optimize delay test quality with a limited size of test setMichiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara. 260 [doi]
• Increasing reliability of programmable mixed-signal systems by applying design diversity redundancyGabriel de M. Borges, Luiz F. Gonçalves, Tiago R. Balen, Marcelo Lubaszewski. 261 [doi]
• Current-based testable design of level shifters in liquid crystal display driversMasaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita. 262 [doi]
• A multi-mode MEMS sensor design to support system test and health & usage monitoring applicationsZ. Xu, A. Richardson, L. Li, M. Begbie, D. Koltsov, C. H. Wang. 263 [doi]
• A new built-in IDDQ testing method using programmable BICSSamed Maltabas, Osman Kubilay Ekekon, Martin Margala. 264 [doi]
• Defect filter for alternate RF testHaralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev. 265-270 [doi]