Table of Contents

• Run-time detection of hardware Trojans: The processor protection unitJeremy Dubeuf, David Hély, Ramesh Karri. 1-6 [doi]
• Novel approach to reduce power droop during scan-based logic BISTMartin Omaña, Daniele Rossi, F. Fuzzi, Cecilia Metra, Chandra Tirumurti, R. Galivache. 1-6 [doi]
• Variability-aware and fault-tolerant self-adaptive applications for many-core chipsGilles Bizot, Fabien Chaix, Nacer-Eddine Zergainoh, Michael Nicolaidis. 1 [doi]
• Computing detection probability of delay defects in signal line tsvsC. Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Vivet, M. Belleville. 1-6 [doi]
• Hybrid 3D pre-bonding test framework designUnni Chandran, Dan Zhao, Rathish Jayabharathi. 1 [doi]
• Experimental evaluation of thread distribution effects on multiple output errors in GPUsPaolo Rech, Caroline Aguiar, Christopher Frost, Luigi Carro. 1-6 [doi]
• Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosisFangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 1-6 [doi]
• Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towersChristos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui. 1-6 [doi]
• Outlook for many-core systems: Cloudy with a chance of virtualizationNikil Dutt. 1 [doi]
• Reconciling the IC test and security dichotomyOzgur Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, Ramesh Karri, Y. Jin, K. Huang, Yiorgos Makris. 1-6 [doi]
• Efficient system-level testing and adaptive tuning of MIMO-OFDM wireless transmittersS. Devarakond, D. Banerjee, A. Banerjee, S. Sen, A. Chatterjee. 1-6 [doi]
• Generation of compact multi-cycle diagnostic test setsIrith Pomeranz. 1 [doi]
• Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?Said Hamdioui, Davide Appello, Arnaud Grasset, Xinli Gu Huawei, Bram Kruseman, Riccardo Mariani, Hermann Obermeir, Srikanth Venkataraman. 1 [doi]
• Efficient fault simulation through dynamic binary translation for dependability analysis of embedded softwareGiuseppe Di Guglielmo, Davide Ferraretto, Franco Fummi, Graziano Pravadelli. 1-6 [doi]
• Reducing power dissipation in memory repair for high defect densitiesPanagiota Papavramidou, Michael Nicolaidis. 1-7 [doi]
• Current testing: Dead or alive?Hans A. R. Manhaeve, Pete Harrod, Adit Singh, Chintan Patel, Ralf Arnolc, Davide Appello. 1 [doi]
• Optimization for timing-speculated circuits by redundancy addition and removalYuxi Liu, Rong Ye, Feng Yuan, Qiang Xu. 1-6 [doi]
• An error-detection and self-repairing method for dynamically and partially reconfigurable systemsMatteo Sonza Reorda, Luca Sterpone, Anees Ullah. 1-7 [doi]
• PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power informationSeetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan, V. Kamakoti. 1 [doi]
• Analyzing resistive-open defects in SRAM core-cell under the effect of process variabilityElena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. 1-6 [doi]
• Bias temperature instability analysis in SRAM decoderSeyab Khan, Said Hamdioui, Halil Kukner, Praveen Raghavan, Francky Catthoor. 1 [doi]
• Implementing model redundancy in predictive alternate test to improve test confidenceHaithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell. 1 [doi]
• Adaptive quality binning for analog circuitsEnder Yilmaz, Sule Ozev, Kenneth M. Butler. 1-6 [doi]
• Error-correction schemes with erasure information for fast memoriesSamuel Evain, Valentin Gherman. 1-6 [doi]
• M-S test based on specification validation using octrees in the measure spaceAlvaro Gómez-Pau, Luz Balado, Joan Figueras. 1-6 [doi]
• New test compression scheme based on low power BISTJerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski. 1-6 [doi]
• A software-based self test of CUDA Fermi GPUsStefano Di Carlo, Giulio Gambardella, Marco Indaco, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta. 1-6 [doi]
• Efficient selection of signatures for analog/RF alternate testManuel J. Barragan Asian, Gildas Leger. 1-6 [doi]
• Test generation for circuits with embedded memories using SMTSarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram. 1 [doi]
• On combining alternate test with spatial correlation modeling in analog/RF ICsKe Huang, Nathan Kupp, John M. Carulli Jr., Yiorgos Makris. 1-6 [doi]
• Semiconductor failure modes and mitigation for critical systems embedded tutorialHans A. R. Manhaeve, Esko Mikkola. 1-3 [doi]
• Utilizing circuit structure for scan chain diagnosisWei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang. 1-6 [doi]
• BIST architecture to detect defects in tsvs during pre-bond testingDaniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras. 1 [doi]
• A minimum MSE sensor fusion algorithm with tolerance to multiple faultsOmid Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, Katarzyna Radecka. 1 [doi]
• Efficient minimization of test frequencies for linear analog circuitsMohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir. 1 [doi]
• A mutual characterization based SAR ADC self-testing techniqueH.-J. Lin, X.-L. Huang, J.-L. Huang. 1-6 [doi]
• Approximate computing: An emerging paradigm for energy-efficient designJie Han, Michael Orshansky. 1-6 [doi]
• Magical thinking applied to test engineering reality (and vice versa)Jeff Rearick. 1 [doi]
• Robust optimization of test-architecture designs for core-based SoCsSergej Deutsch, Krishnendu Chakrabarty. 1-6 [doi]
• Scan pattern retargeting and merging with reduced access timeRafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich. 1-7 [doi]
• RF BIST and test strategy for the receive part of an RF transceiver in CMOS technologyChristophe Kelma, Sébastien Darfeuille, Andreas Neuburger, Andreas Lobnig. 1 [doi]
• Extracting device-parameter variations using a single sensitivity-configurable ring oscillatorYuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif. 1-6 [doi]
• Aggresive scan chain masking for improved diagnosis of multiple scan chain failuresSubhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur. 1 [doi]
• A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testingSaman Kiamehr, Farshad Firouzi, Mehdi Baradaran Tahoori. 1-6 [doi]
• Analytical modeling for EVM in OFDM transmitters including the effects of IIP3, I/Q imbalance, noise, AM/AM and AM/PM distortionAfsaneh Nassery, Sule Ozev, Mustapha Slamani. 1-6 [doi]