Table of Contents

• Tutorial T1B: Riding the "Energy Consumption Horse" - from System-level Design to SiliconPrabhat Avasare, Nitin Chandrachoodan. [doi]
• Keynote talk: Deciphering the brain, cousin to the chipLou Scheffer. [doi]
• Tutorial T10: Post - Silicon Validation, Debug and DiagnosisPrabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal. [doi]
• Keynote talk: Embedded vision systemsVijaykrishnan Narayanan. [doi]
• Embedded tutorial - Emerging memory technologies: What it means for computer system designersMoinuddin K. Qureshi. [doi]
• Embedded tutorial - Can silicon machines match the efficiency of the human brain?Bipin Rajendran. [doi]
• Keynote talk: Opportunities and challenges for high performance microprocessor designs and design automationRuchir Puri. [doi]
• MAPro: A Tiny Processor for Reconfigurable Baseband Modulation MappingLiang Tang, Jude Angelo Ambrose, Sri Parameswaran. 1-6 [doi]
• A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set ProcessorsRoshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran. 7-12 [doi]
• Localized Heating for Building Energy EfficiencyJun Wei Chuah, Chunxiao Li, Niraj K. Jha, Anand Raghunathan. 13-18 [doi]
• Prediction Schemes for Compensating Variable Delay for Improving Performance of Real-Time Control TasksSaptarshi Roy, Amit Patra, Partha Pratim Chakrabarti, Purnendu Sinha, Dipankar Das 0002. 19-24 [doi]
• Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time SystemsRehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao. 25-30 [doi]
• Energy-efficient and Secure Sensor Data Transmission Using EncompressionMeng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha. 31-36 [doi]
• Optimal Pipeline Depth and Supply Voltage for Power-constrained ProcessorsAbhijit Giri, S. K. Nandy. 37-42 [doi]
• CASHIER: A Cache Energy Saving Technique for QoS SystemsSparsh Mittal, Zhao Zhang, Yanan Cao. 43-48 [doi]
• Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore ArchitecturesHadi Hajimiri, Prabhat Mishra, Swarup Bhunia. 49-54 [doi]
• A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell ArchitectureRashmi Sachan, Shahid Ali, Chandan Bist, Sunil Misra, Vinod Menezes, Sharad Gupta, Pat Bosshart. 55-59 [doi]
• Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC PipelineSupriya Aggarwal, Kavita Khare. 60-65 [doi]
• Ultralow-Power and Robust Embedded Memory for Bioimplantable MicrosystemsMaryamsadat Hashemian, Swarup Bhunia. 66-71 [doi]
• A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor NodeAatmesh Shrivastava, Jagdish Nayayan Pandey, Brian P. Otis, Benton H. Calhoun. 72-75 [doi]
• A Novel Scheme to Reset through ClockSanku Mukherjee, M. Thrivikraman M., Anil K. Goyal, Arul Sendhil. 76-79 [doi]
• Impact of Clock-Gating on Power Distribution Network Using Wavelet AnalysisVinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu. 80-85 [doi]
• Design and Implementation of a High Speed MAP Decoder Architecture for Turbo DecodingRahul Shrestha, Roy Paily. 86-91 [doi]
• Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAsB. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan. 92-97 [doi]
• VLSI Implementation of Enhanced Edge Preserving Impulse Noise Removal TechniqueP. Deepa, C. Vasanthanayaki. 98-102 [doi]
• Design of a Fault Tolerant Reversible Compact Unidirectional Barrel ShifterMd. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal, Ahsan Raja Chowdhury. 103-108 [doi]
• A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion DelaysRavi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee. 109-114 [doi]
• Input Referred Offset Reduction in Very High Speed Differential ReceiversRajat Chauhan, Manigandan Selvam. 115-119 [doi]
• Prospects of Near-Threshold Voltage Design for Green ComputingSurhud Khare, Shailendra Jain. 120-124 [doi]
• PODIA: Power Optimization through Differential Imbalanced AmplifierPrashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha. 125-129 [doi]
• A Capacitor-less Low Drop-out (LDO) Regulator with Improved Transient Response for System-on-Chip ApplicationsCheekala Lovaraju, Ashis Maity, Amit Patra. 130-135 [doi]
• A Sub-1V 32nA Process, Voltage and Temperature Invariant Voltage Reference CircuitAnvesha Amaravati, Maryam Shojaei Baghini. 136-141 [doi]
• Area & Power Efficient 3.4Gbps/Channel HDMI Transmitter with Single-Ended StructureNitin Gupta, Phalguni Bala, Vijay Kumar Singh. 142-146 [doi]
• Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient RecoveryNeeraj Mishra, Niraj Jha, Santanu Kapat, Amit Patra. 147-152 [doi]
• Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule EndoscopyBhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi. 153-157 [doi]
• 38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOSPrashant Dubey, Rashmi Agarwal. 158-162 [doi]
• A Wide Range CMOS VCO for PLL ApplicationsAmiya Prasad Behera, Subhasis Sasmal, Prajit Nandi. 163-168 [doi]
• A Fully Integrated CMOS Class-E Power Amplifier for Reconfigurable Transmitters with WCDMA/WiMAX ApplicationsHyuksu Son, Woo Young Kim, Joo Young Jang, Hae Jin Lee, Inn-yeal Oh, Chul Soon Park. 169-172 [doi]
• A 140µA 34ppm/°C 30MHz Clock Oscillator in 28nm CMOS Bulk ProcessAbhirup Lahiri, Anurag Tiwari. 173-178 [doi]
• A 44 GHz Quadrature Traveling Wave OscillatorSomnath Kundu, Shouri Chatterjee. 179-184 [doi]
• Multiphase Technique to Speed-up Delay Measurement via Sub-samplingRajath Vasudevamurthy, Bharadwaj Amrutur. 185-190 [doi]
• Gain, NF and IIP3 Budgeting of LTE Receiver Front EndVinay M. M., Roy Paily, Anil Mahanta. 191-196 [doi]
• Adaptive RF Front-end Design via Self-discovery: Using Real-time Data to Optimize Adaptation ControlDebashis Banerjee, Aritra Banerjee, Abhijit Chatterjee. 197-202 [doi]
• Emerging Frontiers in Embedded SecurityMehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan, Niraj K. Jha. 203-208 [doi]
• Design and Implementation of a High-Speed, Power-Efficient, Modified Hybrid-Mode Sense Amplifier for SRAM ApplicationsDebajit Bhattacharya, Ashis Maity, Amit Patra. 209-214 [doi]
• A Feed-Forward Equalizer for Capacitively Coupled On-Chip InterconnectK. Naveen, Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma. 215-220 [doi]
• Two-Path Quadrature Cascaded Band-Pass Sigma-Delta ModulatorsKumar Y. B. Nithin, Edoardo Bonizzoni, Amit Patra, Franco Maloberti. 221-226 [doi]
• Lifetime Reliability Aware Architectural AdaptationThannirmalai Somu Muthukaruppan, Tulika Mitra. 227-232 [doi]
• Power Supply Efficiency Aware Server Allocation in Data CentersPreeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan. 233-238 [doi]
• Power-Aware Wrappers for Transaction-Level Virtual Prototypes: A Black Box Based ApproachOns Mbarek, Alain Pegatoquet, Michel Auguin, Houssem Eddine Fathallah. 239-244 [doi]
• Measuring Area-Complexity Using Boolean DifferenceAnkit Kagliwal, Shankar Balachandran. 245-250 [doi]
• Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM DecompositionPavlos M. Mattheakis, Christos P. Sotiriou. 251-256 [doi]
• Geometry Independent Wirelength Estimation Method in VLSI RoutingRaka Sardar, Ratna Mondal, Tuhina Samanta. 257-261 [doi]
• Impact of Power Supply Noise on Clock Jitter in High-Speed DDR Memory InterfacesJim Monthie, Vineet Sreekumar, Ranjit Yashwante. 262-266 [doi]
• Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply VoltagesVijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal. 267-272 [doi]
• Reducing Test Time of Power Constrained Test by Optimal Selection of Supply VoltagePraveen Venkataramani, Vishwani D. Agrawal. 273-278 [doi]
• On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test CompressionKazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang. 279-284 [doi]
• Physics Based Fault Models for Testing High-Voltage LDMOSSukeshwar Kannan, Bruce C. Kim, Anurag Gupta, Friedrich Taenzler, Richard Antley, Ken Moushegian. 285-290 [doi]
• Observability-aware Directed Test Generation for Soft Errors and Crosstalk FaultsKanad Basu, Prabhat Mishra, Priyadarsan Patra. 291-296 [doi]
• At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory SystemsSanku Mukherjee, Srinivasaraman Chandrasekaran, Ganapathy Subramanyan E. K., Arul Sendhil. 297-301 [doi]
• Dynamic Trace Signal Selection for Post-Silicon ValidationKihyuk Han, Joon-Sung Yang, Jacob A. Abraham. 302-307 [doi]
• Efficient Signal Selection Using Fine-grained Combination of Scan and Trace BuffersKamran Rahmani, Prabhat Mishra. 308-313 [doi]
• VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature TestsSabyasachi Deyati, Aritra Banerjee, Barry John Muldrey, Abhijit Chatterjee. 314-319 [doi]
• Assertion-Based Functional Consistency Checking between TLM and RTL ModelsMingsong Chen, Prabhat Mishra. 320-325 [doi]
• Formal Verification of Hardware / Software Power Management StrategiesRajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Subhankar Mukherjee. 326-331 [doi]
• Model Checking Controllers with Predicate InputsM. Santhosh Prabhu, Pallab Dasgupta. 332-337 [doi]
• Verification of KPN Level TransformationsChandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal. 338-343 [doi]
• Hardware-corroborated Variability-Aware SRAM MethodologyRajiv V. Joshi, Rouwaida Kanj, S. Butt, Emrah Acar, D. Lea, D. Sciacca. 344-349 [doi]
• Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT VariationsYang Yang, Niraj K. Jha. 350-355 [doi]
• Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical AnalogyYogesh Dilip Save, H. Narayanan, Sachin B. Patkar. 356-361 [doi]
• K-Algorithm: An Improved Booth's Recoding for Optimal Fault-Tolerant Reversible MultiplierKartikeya Bhardwaj, Bharat M. Deshpande. 362-367 [doi]
• A Low Power Fault Tolerant Reversible Decoder Using MOS TransistorsMd. Shamsujjoha, Hafiz Md. Hasan Babu. 368-373 [doi]
• Microelectromechanical Longitudinal Resonator for Frequency Reference ApplicationsRitesh Ray Chaudhuri, Tarun Kanti Bhattacharyya. 374-379 [doi]
• Design and Simulation of Structurally Decoupled 4-DOF MEMS Vibratory GyroscopeAnkush Jain, Ram Gopal. 380-385 [doi]
• Sneak-path Testing of Memristor-based MemoriesSachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu. 386-391 [doi]