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2001

19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USAIEEE Computer Society, 2001.

A Low-Power Asynchronous VLSI FIR FilterV. A. Bartlett, Eckhard Grass. arvlsi 2001: 29-41 [doi]

Focal-Plane Image and Beam Quality Sensors for Adaptive OpticsMarc Cohen, Gert Cauwenberghs, Mikhail Vorontsov, Gary Carhart. arvlsi 2001: 224-237 [doi]

Phantom Mode Signaling in VLSI SystemsThaddeus Gabara. arvlsi 2001: 88-100 [doi]

Analog-Digital Partitioning for Field-Programmable Mixed Signal SystemsSree Ganesan, Ranga Vemuri. arvlsi 2001: 172-187 [doi]

Dynamic Receiver Biasing For Inter-Chip CommunicationClaude R. Gauthier, Jayakumaran Sivagnaname, Richard B. Brown. arvlsi 2001: 101-111 [doi]

Logic Design Considerations for 0.5-Volt CMOSK. Joseph Hass, Jack Venbrux, Prakash Bhatia. arvlsi 2001: 75-87 [doi]

Activity-Sensitive Flip-Flop and Latch Selection for Reduced EnergySeongmoo Heo, Ronny Krashinsky, Krste Asanovic. arvlsi 2001: 59-74 [doi]

A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous SystemsKip C. Killpack, Eric Mercer, Chris J. Myers. arvlsi 2001: 188-201 [doi]

Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic MultiplierSuhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou. arvlsi 2001: 42-58 [doi]

Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFGEuiseok Kim, Jeong-Gun Lee, Dong-Ik Lee. arvlsi 2001: 2-15 [doi]

Dynamic Charge Restoration of Floating Gate Subthreshold MOS Translinear CircuitsVincent F. Koosh, Rodney M. Goodman. arvlsi 2001: 163-171 [doi]

Programmable and Adaptive Analog Filters using Arrays of Floating-Gate CircuitsMatt Kucic, Paul E. Hasler, Jeff Dugger, David V. Anderson. arvlsi 2001: 148-162 [doi]

Visual Sensor with Resolution Enhancement by Mechanical VibrationsOliver Landolt, Ania Mitros, Christof Koch. arvlsi 2001: 249-264 [doi]

Width-Adaptive Data Word ArchitecturesRajit Manohar. arvlsi 2001: 112-131 [doi]

Precise Exceptions in Asynchronous ProcessorsRajit Manohar, Mika Nyström, Alain J. Martin. arvlsi 2001: 16-28 [doi]

Asynchronous Array Multiplier with an Asymmetric Parallel Array StructureChan-Ho Park, Byung-Soo Choi, Dong-Ik Lee, Ho-Yong Choi. arvlsi 2001: 202-212 [doi]

Methods and Circuits for Focal-Plane Computation of Features in CMOS Visual SensorsAlberto Pesavento, Christof Koch. arvlsi 2001: 238-248 [doi]

A High-Performance 64-bit Adder Implemented in Output Prediction LogicSheng Sun, Larry McMurchie, Carl Sechen. arvlsi 2001: 213-223 [doi]

Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOSChris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel. arvlsi 2001: 132-147 [doi]

1999

18th Conference on Advanced Research in VLSI (ARVLSI 99), 21-24 March 1999, Atlanta, GA, USAIEEE Computer Society, 1999.

Area-Universal Circuits with Constant SlowdownSandeep N. Bhatt, Gianfranco Bilardi, Geppino Pucci. arvlsi 1999: 89-98 [doi]

A Throughput-On-Demand Address-Event Transmitter for Neuromorphic ChipsKwabena Boahen. arvlsi 1999: 72-87 [doi]

System-on-a-Chip VLSI - Is It Finally Really Here?Robert W. Brodersen. arvlsi 1999: 154 [doi]

Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel ProcessorSek M. Chai, Antonio Gentile, D. Scott Wills. arvlsi 1999: 57-71 [doi]

Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal CircuitsSudip Chakrabarti, Abhijit Chatterjee. arvlsi 1999: 327-341 [doi]

Architectural Considerations for Application-Specific Counterflow PipelinesBruce R. Childers, Jack W. Davidson. arvlsi 1999: 3-22 [doi]

Exploring Microprocessor Architectures for Gigascale IntegrationLucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl. arvlsi 1999: 242-255 [doi]

Architecture Design of Reconfigurable Pipelined DatapathsDarren C. Cronquist, Chris Fisher, Miguel Figueroa, Paul Franklin, Carl Ebeling. arvlsi 1999: 23-41 [doi]

VLSI Architecture: Past, Present, and FutureWilliam J. Dally, Steve Lacy. arvlsi 1999: 232-241 [doi]

Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino PipelinesAyoob E. Dooply, Kenneth Y. Yun. arvlsi 1999: 200-214 [doi]

MEMS-Based Capacitor Arrays for Programmable Interconnect and RF ApplicationsB. E. Duewer, J. M. Wilson, D. A. Winick, Paul D. Franzon. arvlsi 1999: 369-377 [doi]

Interconnect-Dominated VLSI DesignP. Ghosh, R. Mangaser, C. Mark, K. Rose. arvlsi 1999: 114-122 [doi]

A Quantitative Approach to Nonlinear Process Design Rule ScalingSpencer M. Gold, Richard B. Brown, Bruce Bernhardt. arvlsi 1999: 99-113 [doi]

Adaptive Circuits Using pFET Floating-Gate DevicesPaul E. Hasler, Bradley A. Minch, Chris Diorio. arvlsi 1999: 215-231 [doi]

The Ultrascalar Processor-An Asymptotically Scalable Superscalar MicroarchitectureDana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath. arvlsi 1999: 256-275 [doi]

Multi-Chip Neuromorphic Motion ProcessingCharles M. Higgins, Christof Koch. arvlsi 1999: 309-325 [doi]

Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking ChipTimothy K. Horiuchi, Ernst Niebur. arvlsi 1999: 276-290 [doi]

XXI Century Gigascale Integration (GSI) : The Interconnect ProblemJames D. Meindl. arvlsi 1999: 88 [doi]

Translinear Analog Signal Processing: A Modular Approach to Large-Scale Analog Computation with Multiple-Input Translinear ElementsBradley A. Minch. arvlsi 1999: 186-199 [doi]

A Column-based Processing Array for High-speed Digital Image ProcessingTonia Morris, Erica Fletcher, Cyrus Afghahi, Sami Issa, Kevin Connolly, Jean-Charles Korta. arvlsi 1999: 42-56 [doi]

Problems and Prospects for Electrical SignalingJohn Poulton. arvlsi 1999: 326 [doi]

Silicon Adventures-Go Ahead; Be Bold!Charles L. Seitz. arvlsi 1999: 2 [doi]

Low Power Gate Resizing of Combinational Circuits by Buffer-RedistributionVijay Sundararajan, Keshab K. Parhi. arvlsi 1999: 170-185 [doi]

Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient ComputingNestoras Tzartzanis, William C. Athas. arvlsi 1999: 137-153 [doi]

Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and TestRamakrishna Voorakaranam, Abhijit Chatterjee. arvlsi 1999: 342-357 [doi]

Who Put the Sugar in Sydney Harbor?Neil Weste. arvlsi 1999: 358 [doi]

A Two-Dimensional, Object-Based Analog VLSI Visual Attention SystemCharles S. Wilson, Tonia G. Morris, Stephen P. DeWeerth. arvlsi 1999: 291-308 [doi]

Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven DesignsChing-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang. arvlsi 1999: 155-169 [doi]

Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI CircuitsLi-Rong Zheng, Hannu Tenhunen. arvlsi 1999: 123-136 [doi]

1997

17th Conference on Advanced Research in VLSI (ARVLSI 97), September 15-16, 1997, Ann Arbor, MI, USAIEEE Computer Society, 1997.

A High-Speed Asynchronous Decompression Circuit for Embedded ProcessorsMartin Benes, Andrew Wolfe, Steven M. Nowick. arvlsi 1997: 219-237 [doi]

Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal ProximityV. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi. arvlsi 1997: 32-46 [doi]

Kestrel: Design of an 8-bit SIMD Parallel ProcessorDavid M. Dahle, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Eric Rice, Don Speck, Douglas H. Williams, Richard Hughey. arvlsi 1997: 145 [doi]

A VLSI Architecture for Modeling Intersegmental CoordinationStephen P. DeWeerth, Girish N. Patel, Mario F. Simoni, David E. Schimmel, Ronald L. Calabrese. arvlsi 1997: 182-200 [doi]

Circuits and Technology for Digital s StrongARM(tm) and ALPHA MicroprocessorsDaniel W. Dobberpuhl. arvlsi 1997: 2-11 [doi]

Compact Signed-Digit Adder Using Multiple-Valued LogicAlejandro F. González, Pinaki Mazumder. arvlsi 1997: 96-113 [doi]

Clock Distribution Using Cooperative Ring OscillatorsLes Hall, Mark Clements, Wentai Liu, Griff L. Bilbro. arvlsi 1997: 62-77 [doi]

Image Edge Enhancement, Dynamic Compression and Noise Suppression using Analog Circuit ProcessingTodd Hinck, Allyn E. Hubbard. arvlsi 1997: 114-126 [doi]

Trends of Key Advanced Device TechnologiesB. Chester Hwang. arvlsi 1997: 78-81 [doi]

Asynchronous Microengines for Efficient High-level ControlHans M. Jacobson, Ganesh Gopalakrishnan. arvlsi 1997: 201-218 [doi]

Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-ControlGeorge Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis. arvlsi 1997: 127-144 [doi]

The Design of an Asynchronous MIPS R3000 MicroprocessorAlain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings. arvlsi 1997: 164-181 [doi]

Architectural Design of a Three Dimensional FPGAWaleed Meleis, Miriam Leeser, Paul M. Zavracky, Mankuan Michael Vai. arvlsi 1997: 256-269 [doi]

Circuits and Microarchitecture for Gigahertz VLSI DesignsKevin J. Nowka, H. Peter Hofstee. arvlsi 1997: 284-287 [doi]

Scalability in computing for today and tomorrowDavid Parry. arvlsi 1997: 12-31 [doi]

An Embedded DRAM for CMOS ASICsJohn Poulton. arvlsi 1997: 288-302 [doi]

Next-Generation RF Circuits and SystemsBehzad Razavi. arvlsi 1997: 270-283 [doi]

Fault Scanner for Reconfigurable LogicNathan Shnidman, William H. Mangione-Smith, Miodrag Potkonjak. arvlsi 1997: 238-255 [doi]

Interfacing Synchronous and Asynchronous Modules Within a High-Speed PipelineAllen E. Sjogren, Chris J. Myers. arvlsi 1997: 47-61 [doi]

Design Implementation of Intrinsic Area Array ICsChandra Tan, Donald W. Bouldin, Peyman H. Dehkordi. arvlsi 1997: 82-95 [doi]

The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with ProcessorsTadaaki Yamauchi, Lance Hammond, Kunle Olukotun. arvlsi 1997: 303-319 [doi]

1995

16th Conference on Advanced Research in VLSI (ARVLSI 95), March 27-29, 1995, Chapel Hill, North Carolina, USAIEEE Computer Society, 1995.

A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retinaAndreas G. Andreou, Kwabena Boahen. arvlsi 1995: 225-240 [doi]

Energy recovery for low-power CMOSWilliam C. Athas, Nestoras Tzartzanis. arvlsi 1995: 415-429 [doi]

Abacus: a 1024 processor 8 ns SIMD arrayM. Bolotski, T. Simon, C. Vieri, R. Amirtharajah, Thomas F. Knight Jr.. arvlsi 1995: 28-41 [doi]

Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectricsX. Cai, Keith Nabors, Jacob White. arvlsi 1995: 200-213 [doi]

Silicon VLSI processing architectures incorporating integrated optoelectronic devicesHuy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst. arvlsi 1995: 17-27 [doi]

Low-latency plesiochronous data retimingLarry R. Dennison, William J. Dally, Thucydides Xanthopoulos. arvlsi 1995: 304-315 [doi]

Array-of-arrays architecture for parallel floating point multiplicationH. Dhanesha, K. Falakshahi, Mark Horowitz. arvlsi 1995: 150-157 [doi]

On the performance of level-clocked circuitsCarl Ebeling, Brian Lockyear. arvlsi 1995: 342-357 [doi]

Algorithms for the optimal state assignment of asynchronous state machinesRobert M. Fuhrer, Bill Lin, Steven M. Nowick. arvlsi 1995: 59-75 [doi]

An evaluation of bipartitioning techniquesScott Hauck, Gaetano Borriello. arvlsi 1995: 383-403 [doi]

Single-transistor transparent-latch clockingKei-Yong Khoo, Alan N. Willson Jr.. arvlsi 1995: 331-341 [doi]

Combined DRAM and logic chip for massively parallel systemsPeter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter. arvlsi 1995: 4-16 [doi]

Efficient retiming under a general delay modelKumar N. Lalgudi, Marios C. Papaefthymiou. arvlsi 1995: 368-382 [doi]

A multi-sender asynchronous extension to the AER protocolJohn Lazzaro, John Wawrzynek. arvlsi 1995: 158-171 [doi]

Dynamic CMOS circuit techniques for delay and power reduction in parallel adders Hans Lindkvist, Per Andersson. arvlsi 1995: 121-130 [doi]

Recursive layout generationLouis Monier, Ramsey W. Haddad, Jeremy Dion. arvlsi 1995: 172-184 [doi]

Optimization of combinational and sequential logic circuits for low power using precomputationJosé Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh. arvlsi 1995: 430-444 [doi]

Analog VLSI circuits for manufacturing inspectionTonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth. arvlsi 1995: 241-257 [doi]

A technique for high-speed, fine-resolution pattern generation and its CMOS implementationGary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III. arvlsi 1995: 131-149 [doi]

Automatic synthesis of gate-level timed circuits with choiceChris J. Myers, Tomas Rokicki, Teresa H. Y. Meng. arvlsi 1995: 42-58 [doi]

Distributed synchronous clockingGill A. Pratt, John Nguyen. arvlsi 1995: 316-330 [doi]

HAL: heuristic algorithms for layout synthesisSanjay Rekhi, J. Donald Trotter. arvlsi 1995: 185-199 [doi]

Quasi-algebraic decompositions of switching functionsTed Stanion, Carl Sechen. arvlsi 1995: 358-367 [doi]

Systematic objective-driven computer architecture optimizationTimothy J. Stanley, Trevor N. Mudge. arvlsi 1995: 286-303 [doi]

High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chipsJae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews. arvlsi 1995: 91-107 [doi]

Non-dissipative rail drivers for adiabatic circuitsS. G. Younis, Thomas F. Knight Jr.. arvlsi 1995: 404-414 [doi]

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