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Viewing Publication 1 - 84 from 84

2002

11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA2002.

IWLS2002.

Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI CircuitsAfshin Abdollahi, Farzan Fallah. iwls 2002: 419-424

Symmetry as a Base for a New Decomposition of Boolean LogicAnas Al-Rabadi. iwls 2002: 273-278

Optical Realizations of Reversible LogicAnas Al-Rabadi, Lee W. Casperson. iwls 2002: 21-26

ZBDD-Based Backtrack Search SAT SolverFadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah. iwls 2002: 131-136

Efficient Gate and Input Ordering for Circuit-to-BDD ConversionFadi A. Aloul, Igor L. Markov, Karem A. Sakallah. iwls 2002: 137-142

A Fast Heuristic Algorithm for DisjunctiveTomas Bengtsson, Andrés Martinelli, Elena Dubrova. iwls 2002: 51-56

Implicit Test of Regularity for Not Completely Specified Boolean FunctionsAnna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli. iwls 2002: 345-350

Synthesis of Asynchronous Circuits with Predictable LatencyAlexandre V. Bystrov, Alexandre Yakovlev. iwls 2002: 239-243

An Efficient Two-Level Filter Scheme for Low Power CacheYen-Jen Chang, Feipei Lai, Shanq-Jang Ruan. iwls 2002: 61-66

Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous SystemsTiberiu Chelcea, Steven M. Nowick. iwls 2002: 355-360

Synthesis of Morphable MultipliersSilviu M. S. A. Chiricescu, Michael A. Schuette, Herman Schmit, Robin Glinton. iwls 2002: 109-113

On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL SynthesisGeun Rae Cho, Tom Chen. iwls 2002: 289-294

Enhanced SPFD Rewiring on Improving Rewiring AbilityJason Cong, Joey Y. Lin, Wangning Long. iwls 2002: 91-96

Bi-Decomposition and Tree-Height Reduction for Timing OptimizationJordi Cortadella. iwls 2002: 233-238

Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-NetAnh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin. iwls 2002: 191-196

High-Level Synthesis from the Synchronous Language EsterelStephen A. Edwards. iwls 2002: 401-406

On Low Power High Level Synthesis Using Genetic AlgorithmsMohamed A. Elgamel, Magdy A. Bayoumi. iwls 2002: 37-40

Binary Time Frame ExpansionFarzan Fallah. iwls 2002: 314-319

Technology Mapping for Chemically Assembled Electronic NanotechnologyPetra Färm, Elena Dubrova. iwls 2002: 121-124

The Automatic Generation of Application Specific ProcessorsS. G. Gibb, Laurence E. Turner. iwls 2002: 161-165

Experimental Study on Cell-Base High-Performance Datapath DesignMasanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera. iwls 2002: 283-287

Don t Care Computation in Minimizing Extended Finite State Machines with Presburger ArithmeticYunjian Jiang, Robert K. Brayton. iwls 2002: 327-332

Reducing Multi-Valued Algebraic Operations to BinaryJie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton. iwls 2002: 339-344

On the Verification of Sequential EquivalenceJie-Hong Roland Jiang, Robert K. Brayton. iwls 2002: 307-314

Technology Mapping for Low Leakage Power with Hot-Carrier Effect ConsiderationChang Woo Kang, Massoud Pedram. iwls 2002: 295-300

An Approach to Designing Complex Reversible Logic GatesPawel Kerntopf. iwls 2002: 31-36

Nonlinear Sifting of Decision DiagramsPawel Kerntopf. iwls 2002: 85-90

Low Power Optimization Techniques for BDD Mapped Finite State MachinesMikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton. iwls 2002: 143-148

Reversible Logic Synthesis by Iterative CompositionsAndrei B. Khlopotine, Marek A. Perkowski, Pawel Kerntopf. iwls 2002: 261-266

Field Modifiable Architecture and its Design Methodology: System Design Without Logic SynthesisYoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita. iwls 2002: 103-108

Circuit-Based Evaluation of the Arithmetic Transform of Boolean FunctionsRené Krenz, Elena Dubrova, Andreas Kuehlmann. iwls 2002: 321-326

Metrics for Structural Logic SynthesisPrabhakar Kudva, Andrew Sullivan, William E. Dougherty. iwls 2002: 1-6

A LUT based Approach for High Level Synthesis on FPGAsLoïc Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan. iwls 2002: 167-172

Giga = 1/Nano: CAD Tools and Modeling Challenges for Giga-Scale Mixed Technology Micro-SystemsSteven P. Levitan. iwls 2002: 399

Visualization of Coding Conflicts in Asynchronous Circuit DesignAgnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev. iwls 2002: 155-160

Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell PlacementTheodore W. Manikas, Gerald R. Kane. iwls 2002: 27-30

Modular Partitioning and Dynamic Conjunction Scheduling in Image ComputationChristoph Meinel, Christian Stangier. iwls 2002: 391-396

VisBDD - A Web-based Visualization Framework for OBDD AlgorithmsChristoph Meinel, Harald Sack, Volker Schillings. iwls 2002: 385-390

A Boolean Paradigm in Multi-Valued Logic SynthesisAlan Mishchenko, Robert K. Brayton. iwls 2002: 173-177

Encoding of Boolean Functions and its Application to LUT Cascade SynthesisAlan Mishchenko, Tsutomu Sasao. iwls 2002: 115-120

Simplification of Non-Deterministic Multi-Valued NetworksAlan Mishchenko, Robert K. Brayton. iwls 2002: 333-338

Logic Synthesis of Reversible Wave CascadesAlan Mishchenko, Marek A. Perkowski. iwls 2002: 197-202

Regular Fabrics in Deep Sub-Micron Integrated-Circuit DesignFan Mo, Robert K. Brayton. iwls 2002: 7-12

Overcoming Resolution-Based Lower Bounds for SAT SolversDoRon B. Motter, Igor L. Markov. iwls 2002: 373-378

Net Buffering in the Presence of Multiple Timing ViewsRajeev Murgai. iwls 2002: 367-372

Majority-Based Decomposition of Carry Logic in Binary AddersLeyla Nazhandali, Karem A. Sakallah. iwls 2002: 179-184

Recognition of Transistor Level Complex Sequential and Dynamic Circuits using State Based BDD sFederico Politi. iwls 2002: 221-226

A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet ClassificationAmit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz. iwls 2002: 97-102

Improving Sequential ATPG Using SAT MethodsMukul R. Prasad, Michael S. Hsiao, Jawahar Jain. iwls 2002: 79-84

Optical Systems 101 for EDA PractitionersJaijeet S. Roychowdhury. iwls 2002: 397

Logic Optimization for Asynchronous SI Controllers using Transduction MethodHiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya. iwls 2002: 245-250

Comparison of Decision Diagrams for Multiple-Output Logic FunctionsTsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura. iwls 2002: 379-384

Concurrency in System Level Design: Conflict Between Simulation and Synthesis GoalsNick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta. iwls 2002: 407-411

Comparing Transistor-Level Implementations of 4-Input Logic FunctionsFelipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis. iwls 2002: 361-365

Efficient Layout Synthesis Algorithm for Pass Transistor Logic CircuitsRupesh S. Shelar, Sachin S. Sapatnekar. iwls 2002: 209-214

Reversible Logic Circuit SynthesisVivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes. iwls 2002: 125-130

Topologically Constrained Logic SynthesisSubarnarekha Sinha, Alan Mishchenko, Robert K. Brayton. iwls 2002: 13-20

Timing Analysis for Full-Custom Circuits Using Symbolic DC FormulationsHui-Yuan Song, R. Iris Bahar, Joel Grodstein. iwls 2002: 203-208

Predictability: Definition, Analysis and OptimizationAnkur Srivastava, Majid Sarrafzadeh. iwls 2002: 267-272

Multi-Level Circuit Clustering for Delay MinimizationCliff C. N. Sze, Ting-Chi Wang. iwls 2002: 227-232

Model Generation and Gate Level Abstraction of Complex CMOS Custom Design for Functional and DFT ValidationAmit Tandon, Federico Politi. iwls 2002: 255-260

Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global RoutingHua Tang, Alex Doboli. iwls 2002: 41-44

A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption ConstraintsNattawut Thepayasuwan, Alex Doboli. iwls 2002: 57-60

On-line Error Detection in a Carry-free AdderWhitney J. Townsend, Mitchell A. Thornton, Parag K. Lala. iwls 2002: 251-254

High Throughput Asynchronous Domino Using Dual output BufferMasayuki Tsukisaka, Masashi Imai, Takashi Nanya. iwls 2002: 279-282

Improving Static Ordering of BDDs for Reachability AnalysisJorgiano Vidal, David Déharbe, Dominique Borrione. iwls 2002: 73-77

Optimized Power-Delay Curve Generation for Standard Cell ICsMiodrag Vujkovic, Carl Sechen. iwls 2002: 413-418

A Constructive Matching Algorithm for Library-Based Domino Technology MappingXinning Wang, Prashant Sawkar, Barbara A. Chappell. iwls 2002: 215-220

Linearity of World-Level Circuit Models: New UnderstandingSvetlana N. Yanushkevich, Vlad P. Shmerko, V. D. Malyugin, Piotr Dziurzanski. iwls 2002: 67-72

A Practical Approach to Cycle Bound Estimation for Property CheckingChia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou. iwls 2002: 149-154

Equisolvability of Series vs. Controller s Topology in Synchronous Language EquationsNina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli. iwls 2002: 45-50

A Method for Synthesizing Boolean ConstrainsJun Yuan, Kurt Shultz, John Havlicek, Ken Albin, Adnan Aziz. iwls 2002: 351-353

Simplifying Constraint Solving in Random Simulation GenerationJun Yuan, Ken Albin, Adnan Aziz, Carl Pixley. iwls 2002: 185-190

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2002

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