Journal: IEEE Design & Test of Computers

Volume 13, Issue 4

0 -- 91Wojciech Maly. The future of IC design, testing, and manufacturing
3 -- 0. News
5 -- 0Bernard Courtois. Second Therminic Workshop
6 -- 7Harold S. Stone. Designing in the multimedia era
9 -- 15Stephen Dean Brown. FPGA Architectural Research: A Survey
16 -- 23Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic. Minimizing FPGA Interconnect Delays
24 -- 33Todd A. DeLong, Barry W. Johnson, Joseph A. Profeta III. A Fault Injection Technique for VHDL Behavioral-Level Models
34 -- 39Jacob M. Velixon. Transmission Coefficient Correction for DACs
40 -- 49Karim Arabi, Bozena Kaminska, Janusz Rzeszut. BIST for D/A and A/D Converters
50 -- 60Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. Circular Self-Test Path for FSMs
61 -- 65Jerry M. Soden, Charles F. Hawkins. IDDQ Testing: Issues Present and Future
66 -- 73Koji Nakamae, Homare Sakamoto, Hiromu Fujioka. How ATE Planning Affects LSI Manufacturing Cost
74 -- 81. A D&T Roundtable: Telecommunications System Design
82 -- 85. IEEE Design & Test of Computers 1996 Annual Index, Volume 13
86 -- 87. Author Guidelines IEEE Design & Test of Computers
93 -- 0. Design Automation Technical Committee Newsletter
94 -- 95. Test Technology Tc Newsletter
96 -- 0Robert C. Aitken. When tools cry wolf: Testability pitfalls of synthesized designs

Volume 13, Issue 3

0 -- 112Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov. Panel Summaries
0 -- 144Gil Philips, Yervant Zorian, Charles W. Rosenthal, Bozena Kaminska. Conference Reports
0 -- 0. News
9 -- 11Vijay K. Madisetti, Mark A. Richards. Guest Editors Introduction: Advances in Rapid Prototyping of Digital Systems
12 -- 22Vijay K. Madisetti. Rapid Digital System Prototyping: Current Practice, Future Challenges
32 -- 42Richard M. Sedmak, John S. Evans. Spanning the Product Life Cycle: RASSP DFT
54 -- 65Lan-Rong Dung, Vijay K. Madisetti. Conceptual Prototyping of Scalable Embedded DSP Systems
66 -- 78Sandi Habinc, Peter Sinander. Using VHDL for Board Level Simulation
79 -- 87Harald P. E. Vranken, Marc F. Witteman, Ronald C. van Wuijtswinkel. Design for Testability in Hardware-Software Systems
88 -- 96Ramesh Karri, Karin Högstedt, Alex Orailoglu. Computer-Aided Design of Fault-Tolerant VLSI Systems
98 -- 101Adam Cron. A D&T Special Report: P1149.4 Mixed-Signal Test Bus
102 -- 108. A D&T Roundtable: Deep-Submicron Test in cooperation with the Test Technology Technical Committee
116 -- 117. Design Automation Technical Committee Newsletter
118 -- 119. Test Technology Tc Newsletter
120 -- 0Scott Davidson. How to achieve 95 fault coverage without really trying

Volume 13, Issue 2

0 -- 0Hugo De Man. Submicron design tools: problems and suppliers
2 -- 0Kenneth D. Wagner, Yervant Zorian. EIC Message
3 -- 0Vishwani D. Agrawal. 1995 Asian Test Symposium carves a niche
5 -- 0Ajit M. Prabhu, Richard L. Campbell. Management Perspectives in EDA
8 -- 9Bozena Kaminska, Bernard Courtois. Guest Editors Introduction: Mixed Analog and Digital Systems
10 -- 17Thomas Olbrich, Andrew M. D. Richardson. Design and Self-Test for Switched-Current Building Blocks
18 -- 25Ashok Balivada, Jin Chen, Jacob A. Abraham. Analog Testing with Time Response Parameters
26 -- 33Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi. DC Built-In Self-Test for Linear Analog Circuits
34 -- 41Yukiya Miura. Real-Time Current Testing for A/D Converters
42 -- 57Stephen Dean Brown, Jonathan Rose. FPGA and CPLD Architectures: A Tutorial
58 -- 70Raul San Martin, John P. Knight. Optimizing Power in ASIC Behavioral Synthesis
72 -- 82Paul E. Landman, Renu Mehra, Jan M. Rabaey. An Integrated CAD Environment for Low-Power Design
83 -- 89. A D&T Roundtable Deep-Submicron Design
93 -- 0. Design Automation Technical Committee Newsletter
94 -- 95. Test Technology Tc Newsletter
96 -- 0Scott Davidson. A test puzzle for a TGIF morning

Volume 13, Issue 1

2 -- 0John W. Sheppard. SCC20 attracts IEC participation
3 -- 4Masaharu Imai, Eugenio Villar. ASPDAC 1995: HDL synthesizability and interoperability
5 -- 7Yervant Zorian, Jan Hlavicka. Guest Editors Introduction: East Meets West
8 -- 15Tibor Bartos, Norbert Fristacky. Verifying Timing Consistency in Formal Specifications
16 -- 25Stanislaw J. Piestrak. Self-Checking Design in Eastern Europe
26 -- 35Anatoly Prihozhy. Net Scheduling in High-Level Synthesis
36 -- 46Sergiu Radu, Viorel Onofrei, Mihai Albulet. Interconnection Problems in Modern Computers
48 -- 57Raimund Ubar. Test Synthesis with Alternative Graphs
58 -- 63Mick Tegethoff, Tom Chen. Sensitivity Analysis of Critical Parameters in Board Test
64 -- 69Joseph A. Mielke. Frequency Domain Testing of ADCs
70 -- 78Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth. Fast Power Estimation of Large Circuits
79 -- 81Kenneth M. Thompson. Intel and the Myths of Test
82 -- 83. IEEE Design & Test of Computers
84 -- 85. Design Automation Technical Committee Newsletter
86 -- 87. Test Technology Tc Newsletter
88 -- 0Scott Davidson. Base 1 logic: A method for environmentally friendly PC design