David Esseni - researchr profile publications

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Publications tagged layout

Leakage-Delay Tradeoff in FinFET Logic Circuits: a Comparative Analysis with Bulk TechnologyMatteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi. IEEE Trans. VLSI Syst., 18(2), Feb 2010. [doi]

A Static Layout Algorithm for DiaMetaSonja Maier, Mark Minas. eceasst, 10, 2008. [doi]

An Intelligent Clustering Algorithm for 3D Objects Layouts in Storage SystemsShao-Shin Hung, Hui-Ling Lin. mue 2008: 294-297 [doi]

Efficient Layout of Comic-Like Video SummariesJanko Calic, David P. Gibson, Neill W. Campbell. tcsv, 17(7):931-936, 2007. [doi]

An External Memory Circuit Validation Algorithm for Large VLSI LayoutsYokesh Kumar, Prosenjit Gupta. isvlsi 2007: 510-511 [doi]

Document layout and color driven image retrievalPere Obrador. sigir 2007: 889-890 [doi]

ESD robustness of thin-film devices with different layout structures in LTPS technologyChih-Kang Deng, Ming-Dou Ker. mr, 46(12):2067-2073, 2006. [doi]

Towards Generic Layouts for Multi-Channel Publishing: XF-Extensible Formatting Heli Tervo, Anne Honkaranta, Paula Leinonen. ista 2006: 165-176

Efficient Post-layout Power-Delay Curve GenerationMiodrag Vujkovic, David Wadkins, Carl Sechen. patmos 2005: 393-403 [doi]

Layout of an Arbitrary Permutation in a Minimal Right Triangle AreaMaria Artishchev-Zapolotsky, Shimon Even, Vladimir Yanovski. pdpta 2005: 124-130

Distributed Storage Layout SchemesPeter Sobe. ipps 2005: [doi]

SAN Virtualization Layout and PerformanceBruce McNutt. cmg 2004: 933-940

Supporting Collaborative Layouting in Word ProcessingThomas B. Hodel, Dominik Businger, Klaus R. Dittrich. coopis 2004: 355-372 [doi]

Layout and Content Extraction for PDF DocumentsHui Chao, Jian Fan. das 2004: 213-224 [doi]

Updating Building Layouts of Time-Varying Virtual CitiesMasanobu Honda, Kazunori Mizuno, Yukio Fukui, Seiichi Nishihara. icgi 2004: 365-368 [doi]

Retrieval by Layout Similarity of Documents Represented with MXY TreesFrancesca Cesarini, Simone Marinai, Giovanni Soda. das 2002: 353-364 [doi]

Web User s Interfaces LayoutMarconi Luiz França, Bernardo Lula Jr.. iadis 2002: 491-494

On a solution of a randomized three tracks variant of the Gate Matrix Layout problemMichal Karonski, Magdalena Szymkowiak. DM, 236(1-3):179-189, 2001. [doi]

Turbo recognition: decoding page layoutTaku A. Tokuyasu. JCDL 2001: 475 [doi]

Area efficient layouts of the Batcher sorting networksShimon Even. networks, 38(4):199-208, 2001. [doi]

Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout TechniqueArindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long. dac 1999: 466-471 [doi]

Dynamic spatial layout in graphical user interfacesMaximilian Stempfhuber. hci 1999: 137-141

VP Layout Planning in Survivable ATM NetworksCheng-Shong Wu, Shi-Wei Lee. jise, 15(1):71-89, 1999. [doi]

Pre-layout Delay Calculation Specification for CMOS ASIC LibrariesHisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi. aspdac 1998: 241-248

Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout DataKatsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka. ats 1997: 162-167 [doi]

Layout and Language: Preliminary Investigations in Recognizing the Structure of TablesMatthew Hurst, Shona Douglas. icdar 1997: 1043-1047 [doi]

Improved Parity-Declustered Layouts for Disk ArraysEric J. Schwabe, Ian M. Sutherland. jcss, 53(3):328-343, 1996.

Layout Algorithms for VLSI deisgnAndrea S. LaPaugh. ACM Comput. Surv., 28(1):59-61, 1996.

Wiring Edge-Disjoint LayoutsRuth Kuchem, Dorothea Wagner. gd 1997: 271-285

A Linear Iteration Time Layout Algorithm for Visualising High-Dimensional DataMatthew Chalmers. visualization 1996: 127-132

Recursive layout generationLouis Monier, Ramsey W. Haddad, Jeremy Dion. arvlsi 1995: 172-184 [doi]

Layout synthesis for datapath designsNaveen Buddi, Malgorzata Chrzanowska-Jeske, Charles L. Saxe. eurodac 1995: 86-90 [doi]

Strategic Layout Planning and Simulation for Lean Manufacturing a LayOPT TutorialEric S. Grajo. wsc 1995: 510-514 [doi]

Improved Parity-Declustered Layouts for Disk ArraysEric J. Schwabe, Ian M. Sutherland. spaa 1994: 76-84 [doi]

KLaGen - A Generator of Static CMOS-cell Layout from Circuit SchematicsKarol Doerffer, Attila T. Téby, Oskar Anton, Dieter A. Mlynski. iscas 1993: 1845-1848

ABLE: AMD Backplane for Layout EnginesKenneth W. Wan, Roshan A. Gidwani. dac 1993: 556-560 [doi]

A layout tool for GlotosJ. Song. jss, 21(2):151-162, 1993. [doi]

Layout-by-Example: A Fuzzy Visual Language for Specifying Stereotypes of Diagram LayoutKazuo Sugihara, Kazunari Yamamoto, Kojui Takeda, Mitsuyuki Inaba. vl 1992: 88-94

Generation of Performance Sensitivities for Analog Cell LayoutGeorge Gad-El-Karim, Ronald S. Gyurcsik. dac 1991: 500-505 [doi]

Using Visual Tools for Developing an Asynchronous Parallel Layout AlgorithmDror Zernik, Larry Rudolph. icpp 1991: 280-281

Distributed Layout Verification Using Sequential Software and Standard HardwareYehuda Shiran. itc 1991: 1009-1015

Template Style Considerations for Sea-of-Gates Layout GenerationG. D. Adams, Carlo H. Séquin. dac 1989: 31-36 [doi]

Simulation and layout of a laser radar production facilityS. J. Lehman, W. R. Davison. wsc 1989: 892-895 [doi]

Mismatch simulation for layout sensitive parameters of IC components and devicesGerhard Tröster, Peter Tomaszewski. tcad, 8(2):101-107, 1989. [doi]

A Module Area Estimator for VLSI LayoutXinghao Chen, Michael L. Bushnell. dac 1988: 54-59 [doi]

Parallel Processing and Document LayoutHeather Brown. epodd, 1(2):97-104, 1988.

Symbolic Layout for Bipolar and MOS VLSIKevin S. B. Szabo, James M. Leask, Mohamed I. Elmasry. tcad, 6(2):202-210, 1987. [doi]

A Dynamic and Efficient Representation of Building-Block LayoutWayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh. dac 1987: 376-384 [doi]

Symbolic Layout System: Application Results and Functional ImprovementsM. Terai, Y. Ajioka, T. Noda, M. Ozaki, T. Umeki, K. Sato. tcad, 6(3):346-354, 1987. [doi]

Optimal Layouts of the Tree of Meshes with Vertices on the Perimeter of the Bounding Convex RegionOndrej Sýkora, Imrich Vrto. STACS 1984: 209-217

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