The following publications are possibly variants of this publication:
- A diagnostic test generation procedure for synchronous sequential circuits based on test eliminationIrith Pomeranz, Sudhakar M. Reddy. itc 1998: 1074-1083 [doi]
- ITEM: an iterative improvement test generation procedure for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. glvlsi 2001: 13-18 [doi]
- Test sequences to achieve high defect coverage for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. tcad, 17(10):1017-1029, 1998. [doi]
- On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential CircuitIrith Pomeranz, Sudhakar M. Reddy. TC, 53(9):1121-1133, 2004. [doi]
- On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential CircuitIrith Pomeranz, Sudhakar M. Reddy. vts 2003: 173-178 [doi]
- A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. tcad, 19(5):589-600, 2000. [doi]
- EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverageIrith Pomeranz, Sudhakar M. Reddy. vts 1997: 329-335 [doi]
- Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test StrategyIrith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy. iccad 1991: 454-457
- MIX: A Test Generation System for Synchronous Sequential CircuitsXijiang Lin, Irith Pomeranz, Sudhakar M. Reddy. vlsid 1998: 456-463 [doi]
- Built-in test generation for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. iccad 1997: 421-426 [doi]