Table of Contents

• A 1Kx32 bit WDSRAM page with rapid write accessTheodoras Simopoulos, Themistoklis Haniotakis, George Alexiou. 1-2 [doi]
• Low-energy key exchange for automation systemsDan Kreiser, Zoya Dyka, Ievgen Kabin, Peter Langendörfer. 1-5 [doi]
• Towards novel format for representation of polymorphic circuitsAdam Crha, Vaclav Simek, Richard Ruzicka. 1-2 [doi]
• Optimum polymorphic circuits synthesis methodPetr Fiser, Vaclav Simek. 1-6 [doi]
• Programmable logic for single-output functionsIoannis Voyiatzis, Constantinos Efstathiou, Cleo Sgouropoulou. 1-2 [doi]
• Parallel software-based self-test suite for multi-core system-on-chip: Migration from single-core to multi-core automotive microcontrollersA. Floridia, Davide Piumatti, E. Sanchez, S. De Luca, Alessandro Sansonetti. 1-6 [doi]
• A fully contactless wafer-level testing for UHF RFID tag with on-chip antennaAlessandro Finocchiaro, Giovanni Girlando, Alessandro Motta, Alberto Pagani, Giuseppe Palmisano. 1-6 [doi]
• Increasing reliability of safety critical applications through functional based solutionsErnesto Sanchez. 1 [doi]
• Reconfigurable electrostatically doped 2.5-gate planar field-effect transistors for dopant-free CMOSTillmann Krauss, Frank Wessely, Udo Schwalke. 1-4 [doi]
• Evaluation of a median threshold based EEPROM-PUF concept implemented in a high temperature SOI CMOS technologyBenjamin Willsch, Marius te Heesen, Julia Hauser, Stefan Dreiner, Holger Kappert, Holger Vogt. 1-6 [doi]
• An automatic approach to integration testing for critical automotive softwareJacopo Sini, A. Mugoni, Massimo Violante, A. Quario, C. Argiri, F. Fusetti. 1-2 [doi]
• An alytical modeling of response time and full well capacity of a pinned photo diodeK. Akshay, Parvathy R. Pillai, B. Bhuvan. 1-6 [doi]
• SI ECCS: SECure context saving for IoT devicesEmanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre. 1-2 [doi]
• Dynamic partial reconfiguration verification using assertion based verificationIslam Ahmed, Hassan Mostafa, Ahmed Nader Mohieldin. 1-2 [doi]
• Cross-product functional coverage analysis using machine learning clustering techniquesEman El Mandouh, Ashraf Salem, Mennatallah Amer, Amr G. Wassal. 1-2 [doi]
• Trading-off reliability and performance in FPGA-based reconfigurable heterogeneous systemsAlessandro Vallero, Alberto Carelli, Stefano Di Carlo. 1-6 [doi]
• Impact of dynamic partial reconfiguration on CONNECT Network-on-Chip for FPGAsRamy Ahmed, Hassan Mostafa, A. H. Khalil. 1-5 [doi]
• Analog fault simulation automation at schematic level with random sampling techniquesLiang Wu, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller 0003, Christoph Scheytt, Wolfgang Ecker. 1-4 [doi]
• Methodology for improved event-driven system-level simulation of an RF transceiver subsystem for wireless SoCsFabian Speicher, Christoph Beyerstedt, Markus Scholl, Tobias Saalfeld, Vahid Bonehi, Moritz Schrey, Ralf Wunderlich, Stefan Heinen. 1-4 [doi]
• 3 algorithm with efficient output reorderingS. Kala, Nalesh Sivanandan, Babita R. Jose, Jimson Mathew, Marco Ottavi. 1-2 [doi]
• Numerical approach to predict power device reliabilityAlessandro Sitta, Sebastiano Russo, Gaetano Bazzano, Daniela Cavallaro, Giuseppe Greco 0002, Michele Calabretta. 1-5 [doi]
• A resource-efficient FFT/IFFT architecture for PRIME PLC systemsJing Yang, Nianxiong Tan, Ching-Kae Harris Tzou. 1-2 [doi]
• Ammonia sensors based on in situ fabricated nanocrystalline graphene field-effect devicesD. Noll, Udo Schwalke. 1-5 [doi]
• An energy-autonomous wireless sensor network development platformMichelangelo Grosso, Salvatore Rinaudo, Edoardo Patti, Andrea Acquaviva. 1-6 [doi]
• Wireless sEMG/footswitch driven FPGA embedded digital processor for dynamic MFCV estimationGiovanni Mezzina, Daniela De Venuto. 1-2 [doi]
• Memristor based adaptive impedance and frequency tuning networkChithra Liz Palson, Deepti Das Krishna, Jimson Mathew, Babita Roslind Jose, Marco Ottavi, Vishal Gupta. 1-2 [doi]
• SIC pair generation in near-optimal time with carry-look ahead addersIoannis Voyiatzis, Costas Efstathiou. 1-2 [doi]
• Is aproximate computing suitable for selective hardening of arithmetic circuits?Bastien Deveautour, Arnaud Virazel, P. Girard, Serge Pravossoudovitch, Valentin Gherman. 1-6 [doi]
• Unified field multiplier for ECC: Inherent resistance against horizontal SCA attacksIevgen Kabin, Zoya Dyka, Dan Kreiser, Peter Langendörfer. 1-4 [doi]
• Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facilityMarco Ottavi, Dario Asciolla, Tiziano Fiorucci, Elena Grosso, Carla Marzullo, Alessandro Scaramella, Simone Stramaccioni, Alessia Zibecchi, Carla Andreani, Gian-Carlo Cardarilli, Carlo Cazzaniga, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Pedro Reviriego, Gianluca Furano, Roberto Senesi. 1-4 [doi]
• Device and circuit models of InAlN/GaN D- and dual-gate E-mode HEMTs for design and characterisation of monolithic NAND logic cellAles Chvála, Lukás Nagy, Juraj Marek, Juraj Priesol, Daniel Donoval, Alexander Satka, Michal Blaho, Dagmar Gregusová, Jan Kuzmik. 1-6 [doi]
• A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engineMichael K. Tsiampas, Nestor E. Evmorfopoulos, Konstantis Daloukas, John Moondanos, Georgios I. Stamoulis. 1-6 [doi]
• A novel hardware-accelerated real-time task scheduler based on robust earliest deadline algorithmLukas Kohutka, Viera Stopjaková. 1-2 [doi]
• Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cellsEmna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo. 1-5 [doi]
• Towards a scalable quantum computerCarmen G. Almudéver, Nader Khammassi, L. Hutin, M. Vinet, Masoud Babaie, Fabio Sebastiano, Edoardo Charbon, Koen Bertels. 1 [doi]
• Give me your binary, I'll tell you if it leaksAntoine Bouvet, Nicolas Bruneau, Adrien Facon, Sylvain Guilley, Damien Marion. 1-4 [doi]
• A novel MAC protocol for industrial WLAN: Hardware aspectsZoran Stamenkovic. 1 [doi]
• A configurable operational amplifier based on oxide resistive RAMsH. Aziza, Christian Dufaza, A. Perez. 1-2 [doi]
• The test cost reduction benefits of combining a hierarchical DFT methodology with EDT channel sharing - A case studyBinghua Lu, Selina Sha, Jincheng Wang, Zhigao Zhang, Fanjin Meng, Dragon Hsu, Rick Fisette. 1-4 [doi]