Table of Contents

• The Challenge of Reliability in Future Complex SystemsAndrea Cuomo. 3 [doi]
• Extending Moore s Law into the next Decade - the SER ChallengeNorbert Seifert. 7 [doi]
• Characterizing Laser-Induced Pulses in ICs: Methodology and ResultsDamien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache, Stéphane Rossignol, Pascal Moitrel. 11-16 [doi]
• Path (Min) Delay Faults and Their Impact on Self-Checking Circuits OperationCecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak. 17-22 [doi]
• A New Self-Checking and Code-Disjoint Non-Restoring Array DividerDaniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel. 23-30 [doi]
• Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay SensorSwaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy. 31-36 [doi]
• A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BISTChaowen Yu, Sudhakar M. Reddy, Irith Pomeranz. 37-42 [doi]
• Efficient Deterministic Test Generation for BIST Schemes with LFSR ReseedingStelios Neophytou, Maria K. Michael, Spyros Tragoudas. 43-50 [doi]
• Erratic Effects of Irradiation in Floating Gate Memory CellsG. Cellere, Alessandro Paccagnella, A. Visconti, M. Bonanomi. 51-56 [doi]
• Factors That Impact the Critical Charge of Memory ElementsTino Heijmen, Damien Giot, Philippe Roche. 57-62 [doi]
• Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic CellsG. Hubert, A. Bougerol, F. Miller, N. Buard, Lorena Anghel, T. Carriere, F. Wrobel, R. Gaillard. 63-74 [doi]
• Reliability Issues for Embedded SRAM at 90nm and BelowRobert C. Aitken. 75 [doi]
• Towards The Methodology of On-line DiagnosisRochit Rajsuman. 76 [doi]
• Test Challenges for 3D CircuitsT. M. Mak. 79 [doi]
• Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication NetworkMarcello Coppola. 80 [doi]
• Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC DesignsMagdy S. Abadir. 81 [doi]
• The Consequences of Variability in SoftwareIsaac Levendel. 82 [doi]
• From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately?Lorena Anghel, Michael Nicolaidis, Nadine Buard. 85 [doi]
• Fault Tolerance Implementation within SRAM Based FPGA Design Based upon the Increased Level of Single Event Upset SusceptibilityMelanie Berg. 89-91 [doi]
• Asynchronous Design: Fault Robustness and Security CharacteristicsMarc Renaudin, Yannick Monnet. 92-95 [doi]
• Combinational Logic Soft Error Analysis and ProtectionAndré K. Nieuwland, Samir Jasarevic, Goran Jerin. 99-104 [doi]
• An Improved Technique for Reducing False Alarms Due to Soft ErrorsSandip Kundu, Ilia Polian. 105-110 [doi]
• A Low-Cost Single-Event Latchup Mitigation SschemeMichael Nicolaidis. 111-118 [doi]
• Secure Scan Techniques: A ComparisonDavid Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. 119-124 [doi]
• Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto ProcessorYannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M Buwa Nzenguet. 125-130 [doi]
• Power Attacks on Secure Hardware Based on Early Propagation of DataKonrad J. Kulikowski, Mark G. Karpovsky, Alexander Taubin. 131-138 [doi]
• Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAsMaico Cassel, Fernanda Lima Kastensmidt. 139-144 [doi]
• On-line Fault Detection and Location for NoC InterconnectsCristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande. 145-150 [doi]
• CEDA: Control-flow Error Detection through AssertionsRamtilak Vemu, Jacob A. Abraham. 151-158 [doi]
• On-Line Error Detection in Wireless RF Transmitters Using Real-time Streaming DataV. Natarajan, G. Srinivasan, A. Chatterjee. 159-164 [doi]
• Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case StudyCristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel. 165-172 [doi]
• Embedded Borden 2-UED Code CheckersSteffen Tarnick. 173-175 [doi]
• A Note on Error Detection in an RSA Architecture by Means of Residue CodesLuca Breveglieri, Paolo Maistri, Israel Koren. 176-177 [doi]
• Localization of Faults in Radix-n Signed Digit AddersGian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano. 178-180 [doi]
• Embedded Scan Test with Diagnostic Features for Self-Testing SoCsChristian Galke, René Kothe, S. Schultke, K. Winkler, J. Honko, Heinrich Theodor Vierhaus. 181-182 [doi]
• Emulation-based Fault Injection in Circuits with Embedded MemoriesMario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena. 183-184 [doi]
• Fault Tolerant System Design Method Based on Self-Checking CircuitsPavel Kubalík, Petr Fiser, Hana Kubatova. 185-186 [doi]
• Built-in Self Repair by Reconfiguration of FPGAsS. Habermann, René Kothe, Heinrich Theodor Vierhaus. 187-188 [doi]
• Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric DevicesLuca Sterpone, Massimo Violante. 189-190 [doi]
• Evaluating SEU and Crosstalk Effects in Network-on-Chip RoutersArthur Pereira Frantz, Luigi Carro, Érika F. Cota, Fernanda Lima Kastensmidt. 191-192 [doi]
• Diophantine-Equation Based Arithmetic Test Set EmbeddingDimitris Nikolos, Dimitrios Kagaris, Spyros Gidaros. 193-194 [doi]
• Design of a Robust 8-Bit Microprocessor to Soft ErrorsRodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis. 195-196 [doi]
• Should Logic SER be Solved at the Circuit Level?T. M. Mak, Subhasish Mitra. 199 [doi]
• DMT and DT2: Two Fault-Tolerant Architectures developed by CNES for COTs-based Spacecraft SupercomputersMichel Pignol. 203-212 [doi]
• Fault-Robust Microcontrollers for Automotive ApplicationsRiccardo Mariani, Peter Fuhrmann, Boris Vittorelli. 213-218 [doi]
• Contribution of Communications to Dependability in Massively-Defective General-Purpose NanoarchitecturesJacques Henri Collet, Piotr Zajac, Yves Crouzet, Andrzej Napieralski. 219-228 [doi]
• Hardware-in-the-Loop-Based Dependability Analysis of Automotive SystemsMatteo Sonza Reorda, Massimo Violante. 229-234 [doi]
• A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAsP. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis. 235-241 [doi]
• Real Time Fault Injection Using a Modified Debugging InfrastructureAndré V. Fidalgo, Gustavo R. Alves, José M. Ferreira. 242-250 [doi]
• The Problem of On-Line Testing Methods In Approximate Data ProcessingAlexander V. Drozd, M. V. Lobachev, J. V. Drozd. 251-256 [doi]
• Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature SchemesMarcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira. 257-262 [doi]
• Online Testing by Protocol DecompositionDeepali Koppad, Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev. 263-268 [doi]
• Soft Error Rates in Deep-Submicron CMOS TechnologiesTino Heijmen. 271 [doi]
• Trend in DRAM Soft ErrorsGünter Schindlbeck. 272 [doi]
• Checker No-Harm Alarm RobustnessDaniele Rossi, Martin Omaña, Cecilia Metra, Andrea Pagni. 275-280 [doi]
• Designing Robust Checkers in the Presence of Massive Timing ErrorsFrederic Worm, Patrick Thiran, Paolo Ienne. 281-286 [doi]
• Error Correction in Arithmetic Operations by I/O InversionPetros Oikonomakos, Paul Fox. 287-292 [doi]