Table of Contents

• Learning heuristics by genetic algorithmsRolf Drechsler, Bernd Becker. [doi]
• Implicit prime compatible generation for minimizing incompletely specified finite state machinesHiroyuki Higuchi, Yusuke Matsunaga. [doi]
• Search space reduction in high level synthesis by use of an initial circuitAtsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, Masatoshi Sekine. [doi]
• Electronic data book: current status of standard representation and future perspectiveKinya Tabuchi. [doi]
• Synthesis of false loop free circuitsShih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang. [doi]
• A CSIC implementation with POCSAG decoder and microcontroller for paging applicationsJ. Y. Lim, G. Kim, I.-S. O, J. H. Cho, Y. Kim, H. Y. Kim. [doi]
• Assessing the feasibility of interface designs before their implementationMarco A. Escalante, Nikitas J. Dimopoulos. [doi]
• Design automation for integrated continuous-time filters using integratorsKazuyuki Wada, Shigetaka Takagi, Zdzislaw Czarnul, Nobuo Fujii. [doi]
• A hardware-oriented design for weighted median filtersChun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao. [doi]
• A new K-way partitioning approach for multiple types of FPGAsBernhard M. Riess, Heiko A. Giselbrecht, Bernd Wurth. [doi]
• Automatic design for bit-serial MSPA architectureHiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito. [doi]
• A robust min-cut improvement algorithm based on dynamic look-ahead weightingKatsunori Tani. [doi]
• A tool for measuring quality of test pattern for LSIs functional designTakashi Aoki, Tomoji Toriyama, Kenji Ishikawa, Kennosuke Fukami. [doi]
• Power analysis of a 32-bit embedded microcontrollerVivek Tiwari, Mike Tien-Chien Lee. [doi]
• Synthesis and simulation of digital demodulator for infrared data communicationHiroshi Uno, Toru Chiba, Keiji Kumatani, Isao Shirakawa. [doi]
• A layout approach to Monolithic Microwave ICAkira Nagao, Chiyoshi Yoshioka, Takashi Kambe, Isao Shirakawa. [doi]
• EDIF version 350/400 and information modelingHilary J. Kahn. [doi]
• Region definition and ordering assignment with the minimization of the number of switchboxesJin-Tai Yan. [doi]
• Synthesis-for-testability using transformationsMiodrag Potkonjak, Sujit Dey, Rabindra K. Roy. [doi]
• A scheduling algorithm for synthesis of bus-partitioned architecturesVasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru. [doi]
• Generic fuzzy logic CAD development toolEric Q. Kang, Eugene Shragowitz. [doi]
• Optimum PLA folding through boolean satisfiabilityJosé M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas. [doi]
• Techniques for low power realization for FIR filtersMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. [doi]
• A new performance driven placement method with the Elmore delay model for row based VLSIsTetsushi Koide, Mitsuhiro Ono, Shin ichi Wakabayashi, Yutaka Nishimaru. [doi]
• A new system partitioning method under performance and physical constraints for multi-chip modulesYoshinori Katsura, Tetsushi Koide, Shin ichi Wakabayashi, Noriyoshi Yoshida. [doi]
• Logic rectification and synthesis for engineering changeChih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen. [doi]
• A model-adaptable MOSFET parameter extraction systemMasaki Kondo, Hidetoshi Onodera, Keikichi Tamaru. [doi]
• Reclocking for high-level synthesisPradip K. Jha, Nikil D. Dutt, Sri Parameswaran. [doi]
• A hardware-software co-simulator for embedded system design and debuggingA. Ghosh, M. Bershteyn, R. Casley, C. Chien, A. Jain, M. Lipsie, D. Tarrodaychik, O. Yamamo. [doi]
• Power recduction by gate sizing with path-oriented slack calculationHow-Rern Lin, TingTing Hwang. [doi]
• System-level verification of CDMA modem ASICGyeong Lyong Park, Kyung Hi Chang, Jae Seok Kim, Kyung Soo Kim. [doi]
• Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functionsChip-Hong Chang, Bogdan J. Falkowski. [doi]
• A hardware/software codesign method for pipelined instruction set processor using adaptive databaseNguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi. [doi]
• Timing influenced generell-cell genetic floorplannerSadiq M. Sait, Habib Youssef, Shahid K. Tanvir, Muhammad S. T. Benten. [doi]
• Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimizationNozomu Togawa, Masao Sato, Tatsuo Ohtsuki. [doi]
• Fanout-tree restructuring algorithm for post-placement timing optimizationT. Aoki, Masami Murakata, Takashi Mitsuhashi, Nobuyuki Goto. [doi]
• Pin assignment and routing on a single-layer Pin Grid ArrayMan-Fai Yu, Wayne Wei-Ming Dai. [doi]
• Routing on regular segmented 2-D FPGAsYu-Liang Wu, Malgorzata Marek-Sadowska. [doi]
• A new layout synthesis for leaf cell designMasahiro Fukui, Noriko Shinomiya, Toshiro Akino. [doi]
• A three-layer over-cell multi-channel routing method for a new cell modelMasahiro Tsuchiya, Tetsushi Koide, Shin ichi Wakabayashi, Noriyoshi Yoshida. [doi]
• Improved computational methods and lazy evaluation of the Ordered Ternary Decision DiagramPer Lindgren. [doi]
• Delay abstraction in combinational logic circuitsNoriya Kobayashi, Sharad Malik. [doi]
• A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problemsC.-J. Richard Shi, Janusz A. Brzozowski. [doi]
• Transistor reordering rules for power reduction in CMOS gatesWen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang. [doi]
• A new and accurate interconnection delay time evaluation in a general tree-type networkDenis Deschacht, Christophe Dabrin. [doi]
• Communication based FPGA synthesis for multi-output Boolean functionsChristoph Scholl, Paul Molitor. [doi]
• A digital audio signal processor for cellular phone applicationJeongsik Yang, Chanhong Park, Beomsup Kim. [doi]
• On hazard-free implementation of speed-independent circuitsAlex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev. [doi]
• A neural network approach to the placement problemMorteza Saheb Zamani, Graham R. Hellestrand. [doi]
• Technology mapping for FPGAs with complex block architectures by fuzzy logic techniquesJung-Yong Lee, Eugene Shragowitz. [doi]
• Limits of using signatures for permutation independent Boolean comparisonJanett Mohnke, Paul Molitor, Sharad Malik. [doi]
• How sub-micron delay and timing issues will be solved?Hitoshi Yoshizawa. [doi]
• Extending pitchmaking algorithms to layouts with multiple grid constraintsHiroshi Miyashita. [doi]
• Exploitation signal flow and logic dependency in standard cell placementJason Cong, Dongmin Xu. [doi]
• Optimization methods for lookup-table-based FPGAs using transduction methodShigeru Yamashita, Yahiko Kambayashi, Saburo Muroga. [doi]
• A scheduling algorithm for multiport memory minimization in datapath synthesisHae-Dong Lee, Sun Young Hwang. [doi]
• A datapath synthesis system for the reconfigurable datapath architectureReiner W. Hartenstein, Rainer Kress. [doi]
• High-level synthesis scheduling and allocation using genetic algorithmsMarc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess. [doi]
• Integrated interconnect circuit modeling for VLSI designWon-Young Jung, Ghun-Up Cha, Young-Bae Kim, Jun-Ho Baek, Choon-Kyung Kim. [doi]
• GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressionsDebatosh Debnath, Tsutomu Sasao. [doi]
• Performance-driven circuit partitioning for prototyping by using multiple FPGA chipsChunghee Kim, Hyunchul Shin, Young-Uk Yu. [doi]
• Future direction of synthesizabilty and interoperability of HDL s: part 2Eugenio Villar, Masaharu Imai. [doi]
• Manipulation of regular expressions under length constraints using zero-suppressed-BDDsShinya Ishihara, Shin-ichi Minato. [doi]
• Current and charge estimation in CMOS circuitsSanjay Dhar, Dave J. Gurney. [doi]
• Design automation 2000 (panel session): challenges for gigabit-eraRichard K. Wallace. [doi]
• Some remarks about spectral transform interpretation of MTBDDs and EVBDDsRadomir S. Stankovic. [doi]
• Performance driven multiple-source bus synthesis using buffer insertionChia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin. [doi]
• BIST with negligible aliasing through random cover circuitsT. Bogue, Helmut Jürgensen, Michael Gössel. [doi]
• Future direction of synthesizability and interoperability of HDL s: part 1Masaharu Imai, Eugenio Villar. [doi]
• Auriga2: a 4.7 million-transistor CISC microprocessorJ. P. Tual, M. Thill, C. Bernard, Huy Nam Nguyen, F. Mottini, M. Moreau, P. Vallet. [doi]
• A design of high-performance multiplier for digital video transmissionKeisuke Okada, Shun Morikawa, Isao Shirakawa, Sumitaka Takeuchi. [doi]
• Logic optimization by an improved sequential redundancy addition and removal techniquesUwe Gläser, Kwang-Ting Cheng. [doi]
• Stoht: an SDL-to-hardware translatorIvanil S. Bonatti, Renato J. O. Figueiredo. [doi]
• A built-in self test scheme for VLSIT. Raju Damarla, Wei Su, Gerald T. Michael, Moon J. Chung, Charles E. Stroud. [doi]
• An integrated hardware-software cosimulation environment for heterogeneous systems prototypingYongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha. [doi]
• An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctutationMikako Miyama, Goichi Yokomizo, Masato Iwabuchi, Masami Kinoshita. [doi]
• Design for testability using register-transfer level partial scan selectionAkira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka. [doi]
• Architectural simulation for a programmable DSP chip setJong Tae Lee, Jaemin Kim, Jae Cheol Son. [doi]
• EMPAR: an interactive synthesis environment for hardware emulationsWen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee. [doi]