Table of Contents

• Package and Interconnect Modeling of the HFA3624, a 2.4GHz RF to IF ConverterMattan Kamon, Steve S. Majors. 2-7 [doi]
• HEAT: Hierarchical Energy Analysis ToolJanardhan H. Satyanarayana, Keshab K. Parhi. 9-14 [doi]
• Opportunities and Obstacles in Low-Power System-Level CADAndrew Wolfe. 15-20 [doi]
• POSE: Power Optimization and Synthesis EnvironmentSasan Iman, Massoud Pedram. 21-26 [doi]
• Early Power Exploration - A World Wide Web ApplicationDavid Lidsky, Jan M. Rabaey. 27-32 [doi]
• Behavioral SynthesisRaul Camposano. 33-34 [doi]
• A Register File and Scheduling Model for Application Specific Processor SynthesisEhat Ercanli, Christos A. Papachristou. 35-40 [doi]
• Optimized Code Generation of Multiplication-free Linear TransformsMahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar. 41-46 [doi]
• Concurrent Analysis Techniques for Data Path Timing OptimizationChuck Monahan, Forrest Brewer. 47-50 [doi]
• HDL Optimization Using Timed Decision TablesJian Li, Rajesh K. Gupta. 51-54 [doi]
• Efficient Partial Enumeration for Timing Analysis of Asynchronous SystemsEric Verlind, Gjalt G. de Jong, Bill Lin. 55-58 [doi]
• Verification of asynchronous circuits using Time Petri Net unfoldingAlexei L. Semenov, Alexandre Yakovlev. 59-62 [doi]
• Methodology and Tools for State Encoding in Asynchronous Circuit SynthesisJordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev. 63-66 [doi]
• A Technique for Synthesizing Distributed Burst-mode CircuitsPrabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson. 67-70 [doi]
• Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level LogicMichael Theobald, Steven M. Nowick, Tao Wu. 71-76 [doi]
• Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input ChangesPrabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick. 77-82 [doi]
• Partitioning of VLSI Circuits and SystemsFrank M. Johannes. 83-87 [doi]
• New Spectral Linear Placement and Clustering ApproachJianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng. 88-93 [doi]
• Characterization and Parameterized Random Generation of Digital CircuitsMichael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil. 94-99 [doi]
• A Probability-Based Approach to VLSI Circuit PartitioningShantanu Dutt, Wenyong Deng. 100-105 [doi]
• Verification of Electronic SystemsAlberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha. 106-111 [doi]
• Design Considerations and Tools for Low-voltage Digital System DesignAnantha Chandrakasan, Isabel Yang, Carlin Vieri, Dimitri Antoniadis. 113-118 [doi]
• VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic SystemsBernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser. 119-124 [doi]
• A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit SimulationMadhav P. Desai, Yao-Tsung Yen. 125-130 [doi]
• Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture SynthesisBalakrishnan Iyer, Ramesh Karri. 137-142 [doi]
• Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI SystemsAntonio R. W. Todesco, Teresa H. Y. Meng. 149-154 [doi]
• Compact Vector Generation for Accurate Power SimulationShi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee. 161-164 [doi]
• Improving the Efficiency of Power Simulators by Input Vector CompactionChi-Ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram. 165-168 [doi]
• Efficient Communication in a Design EnvironmentIdalina Videira, Paulo Veríssimo, Helena Sarmento. 169-174 [doi]
• A Description Language for Design Process ManagementPeter R. Sutton, Stephen W. Director. 175-180 [doi]
• Improved Tool and Data Selection in Task ManagementJohn W. Hagerman, Stephen W. Director. 181-184 [doi]
• Application of a Markov Model to the Measurement, Simulation, and Diagnosis of an Iterative Design ProcessEric W. Johnson, Luis A. Castillo, Jay B. Brockman. 185-188 [doi]
• Tutorial: Design of a Logic Synthesis SystemRichard L. Rudell. 191-196 [doi]
• On Solving Covering ProblemsOlivier Coudert. 197-202 [doi]
• A New Complete Diagnosis Patterns for Wiring InterconnectsSungju Park. 203-208 [doi]
• A Satisfiability-Based Test Generator for Path Delay Faults in Combinational CircutsChih-Ang Chen, Sandeep K. Gupta. 209-214 [doi]
• On Static Compaction of Test Sequences for Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 215-220 [doi]
• An ::::O(n):::: Algorithm for Transistor Stacking with Performance ConstraintsBulent Basaran, Rob A. Rutenbar. 221-226 [doi]
• Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC DesignPaolo Miliozzi, Iasson Vassiliou, Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli. 227-232 [doi]
• Equation-Based Behavioral Model Generation for Nonlinear Analog CircuitsCarsten Borchers, Lars Hedrich, Erich Barke. 236-239 [doi]
• Multilevel Logic Synthesis for Arithmetic FunctionsChien-Chung Tsai, Malgorzata Marek-Sadowska. 242-247 [doi]
• Synthesis by Spectral Translation Using Boolean Decision DiagramsJeffery P. Hansen, Masatoshi Sekine. 248-253 [doi]
• Delay Minimal Decomposition of Multiplexers in Technology MappingShashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy. 254-257 [doi]
• Error Correction Based on Verification TechniquesShi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng. 258-261 [doi]
• Layout Driven Selecting and Chaining of Partial ScanChau-Shen Chen, Kuang-Hui Lin, TingTing Hwang. 262-267 [doi]
• Test Point Insertion: Scan Paths through Combinational LogicChih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee. 268-273 [doi]
• Area Efficient Pipelined Pseudo-Exhaustive Testing with RetimingHuoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng. 274-279 [doi]
• Stable and Efficient Reduction of Large, Multiport RC Networks by Pole Analysis via Congruence TransformationsKevin J. Kerns, Andrew T. Yang. 280-285 [doi]
• Efficient AC and Noise Analysis of Two-Tone RF CircuitsRicardo Telichevesky, Kenneth S. Kundert, Jacob White. 292-297 [doi]
• Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend StrategiesL. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen. 298-303 [doi]
• Code Generation and Analysis for the Functional Verification of MicroprocessorsAnoosh Hosseini, Dimitrios Mavroidis, Pavlos Konas. 305-310 [doi]
• Hardware Emulation for Functional Verification of K5Gopi Ganapathy, Ram Narayan, Glenn Jorden, Denzil Fernandez, Ming Wang, Jim Nishimura. 315-318 [doi]
• Functional Verification Methodology for the PowerPC 604 MicroprocessorJames Monaco, David Holloway, Rajesh Raina. 319-324 [doi]
• Glitch Analysis and Reduction in Register Transfer LevelAnand Raghunathan, Sujit Dey, Niraj K. Jha. 331-336 [doi]
• An Effective Power Management Scheme for RTL Design Based on Multiple ClocksChristos A. Papachristou, Mark Spining, Mehrdad Nourani. 337-342 [doi]
• Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based ApproachMani B. Srivastava, Miodrag Potkonjak. 343-348 [doi]
• Scheduling Techniques to Enable Power ManagementJosé Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar. 349-352 [doi]
• Electromigration Reliability Enhancement via Bus Activity DistributionAurobindo Dasgupta, Ramesh Karri. 353-356 [doi]
• A Sparse Image Method for BEM Capacitance ExtractionByron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi. 357-362 [doi]
• A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity AnalysisNarayan R. Aluru, V. B. Nadkarni, James White. 363-366 [doi]
• Multipole Accelerated Capacitance Calculation for Structures with Multiple Dielectrics with high Permittivity RatiosJohannes Tausch, Jacob K. White. 367-370 [doi]
• Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of InvarianceWeikai Sun, Wayne Wei-Ming Dai, Wei Hong II. 371-376 [doi]
• Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral TransformsJoel R. Philips, Eli Chiprout, David D. Ling. 377-382 [doi]
• Useful-Skew Clock Routing With Gate Sizing for Low Power DesignJoe G. Xi, Wayne Wei-Ming Dai. 383-388 [doi]
• Sizing of Clock Distribution Networks for High Performance CPU ChipsMadhav P. Desai, Radenko Cvijetic, James Jensen. 389-394 [doi]
• New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire SizingJohn Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho. 395-400 [doi]
• Constructing Lower and Upper Bounded Delay Routing Trees Using Linear ProgrammingJaewon Oh, Iksoo Pyo, Massoud Pedram. 401-404 [doi]
• Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian RelaxationChung-Ping Chen, Yao-Wen Chang, D. F. Wong. 405-408 [doi]
• How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work TogetherRobert C. Hutchins, Shankar Hemmady. 409-414 [doi]
• Functional Verification Methodology of Chameleon ProcessorFrançoise Casaubieilh, Anthony McIsaac, Mike Benjamin, Mike Bartley, François Pogodalla, Frédéric Rocheteau, Mohamed Belhadj, Jeremy Eggleton, Gérard Mas, Geoff Barrett, Christian Berthet. 421-426 [doi]
• Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD ToolsStephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic. 427-432 [doi]
• Power Estimation of Cell-Based CMOS CircuitsAlessandro Bogliolo, Luca Benini, Bruno Riccò. 433-438 [doi]
• A New Hybrid Methodology for Power EstimationDavid Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska. 439-444 [doi]
• A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational CircuitsYong Je Lim, Kyung-Im Son, Heung-Joon Park, Mani Soma. 445-450 [doi]
• Engineering Change in a Non-Deterministic FSM SettingSunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 451-456 [doi]
• Identifying Sequential Redundancies Without SearchMahesh A. Iyer, David E. Long, Miron Abramovici. 457-462 [doi]
• A Fast State Reduction Algorithm for Incompletely Specified Finite State MachinesHiroyuki Higuchi, Yusuke Matsunaga. 463-466 [doi]
• Symbolic Optimization of FSM Networks Based on Sequential ATPG TechniquesFabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto. 467-470 [doi]
• Module Compaction in FPGA-based Regular DatapathsAndreas Koch. 471-476 [doi]
• Network Partitioning into Tree Hierarchies477-482 [doi]
• Efficient Approximation Algorithms for Floorplan Area MinimizationDanny Z. Chen, Xiaobo Hu. 483-486 [doi]
• Optimal Wire-Sizing Formular Under the Elmore Delay ModelChung-Ping Chen, Yao-Ping Chen, D. F. Wong. 487-490 [doi]
• VLSI Design and System Level Verification for the Mini-DiscTetsuya Fujimoto, Takashi Kambe. 491-496 [doi]
• Design Methodologies for consumer-use video signal processing LSIsHisakazu Edamatsu, Satoshi Ikawa, Katsuya Hasegawa. 497-502 [doi]
• Issues and Answers in CAD Tool InteroperabilityMike Murray, Uwe B. Meding, Bill Berg, Yatin Trivedi, Bill McCaffrey, Ted Vucurevich. 509-514 [doi]
• The Design of Mixed Hardware/Software SystemsJay K. Adams, Donald E. Thomas. 515-520 [doi]
• Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW ApplicationsSteven Vercauteren, Bill Lin, Hugo De Man. 521-526 [doi]
• A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate CountsNguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi. 527-532 [doi]
• Analysis of RC Interconnections Under Ramp InputAndrew B. Kahng, Sudhakar Muddu. 533-538 [doi]
• An AWE Technique for Fast Printed Circuit Board DelaysBernard N. Sheehan. 539-543 [doi]
• RC-Interconnect Macromodels for Timing SimulationFlorentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi. 544-547 [doi]
• iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI ChipsYi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang. 548-551 [doi]
• Techniques for Verifying Superscalar MicroprocessorsJerry R. Burch. 552-557 [doi]
• A Scalable Formal Verification Methodology for Pipelined MicroprocessorsJeremy R. Levitt, Kunle Olukotun. 558-563 [doi]
• State Reduction Using Reversible RulesC. Norris Ip, David L. Dill. 564-567 [doi]
• Formal Verification of Embedded Systems based on CFSM NetworksFelice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 568-571 [doi]
• Combined Control Flow Dominated and Data Flow Dominated High-Level SynthesisElisabeth Berrebi, Polen Kission, Serge Vernalde, S. De Troch, Jean-Claude Herluison, Jean Fréhel, Ahmed Amine Jerraya, Ivo Bolsens. 573-578 [doi]
• Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDLMike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita. 585-590 [doi]
• Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register ArchitecturesGuido Araujo, Sharad Malik, Mike Tien-Chien Lee. 591-596 [doi]
• Address Calculation for Retargetable Compilation and Exploration of Instruction-Set ArchitecturesClifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya. 597-600 [doi]
• Analysis of Operation Delay and Execution Rate Constraints for Embedded SystemsRajesh K. Gupta. 601-604 [doi]
• Efficient Software Performance Estimation Methods for Hardware/Software CodesignKei Suzuki, Alberto L. Sangiovanni-Vincentelli. 605-610 [doi]
• An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse ResponseBogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi. 611-616 [doi]
• Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition TimeV. Chandramouli, Karem A. Sakallah. 617-622 [doi]
• Optimal Clock Skew Scheduling Tolerant to Process VariationsJosé Luis Neves, Eby G. Friedman. 623-628 [doi]
• An Efficient Equivalence Checker for Combinational CircuitsYusuke Matsunaga. 629-634 [doi]
• High Performance BDD Package By Exploiting Memory HiercharchyJagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 635-640 [doi]
• Implementation of an Efficient Parallel BDD PackageTony Stornetta, Forrest Brewer. 641-644 [doi]
• Word Level Model Checking - Avoiding the Pentium FDIV ErrorEdmund M. Clarke, Manpreet Khaira, Xudong Zhao. 645-648 [doi]
• Formal Verification of PowerPC Arrays Using Symbolic Trajectory EvaluationManish Pandey, Richard Raimi, Derek L. Beatty, Randal E. Bryant. 649-654 [doi]
• RuleBase: An Industry-Oriented Formal Verification ToolIlan Beer, Shoham Ben-David, Cindy Eisner, Avner Landver. 655-660 [doi]
• Bit-Level Analysis of an SRT Divider CircuitRandal E. Bryant. 661-665 [doi]
• Integrating Formal Verification Methods with A Conventional Project Design FlowÁsgeir Th. Eiríksson. 666-671 [doi]
• A System Design Methodology for Software/Hardware Co-Development of Telecommunication Network ApplicationsBill Lin. 672-677 [doi]
• A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded ArchitecturesSteven Vercauteren, Bill Lin, Hugo De Man. 678-683 [doi]
• Software Development in a Hardware Simulation EnvironmentBenny Schnaider, Einat Yogev. 684-689 [doi]
• Compiled HW/SW Co-SimulationVojin Zivojnovic, Heinrich Meyr. 690-695 [doi]
• Stochastic Sequential Machine Synthesis Targeting Constrained Sequence GenerationDiana Marculescu, Radu Marculescu, Massoud Pedram. 696-701 [doi]
• Energy Characterization based on ClusteringHuzefa Mehta, Robert Michael Owens, Mary Jane Irwin. 702-707 [doi]
• Architectural Retiming: Pipelining Latency-Constrained CircutsSoha Hassoun, Carl Ebeling. 708-713 [doi]
• Optimizing Systems for Effective Block-Processing: The ::::k::::-Delay ProblemKumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak. 714-719 [doi]
• Optimal Clock Period FPGA Technology Mapping for Sequential CircuitsPeichen Pan, C. L. Liu. 720-725 [doi]
• Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA DesignJason Cong, Yean-Yow Hwang. 726-729 [doi]
• New Algorithms for Gate Sizing: A Comparative StudyOlivier Coudert, Ramsey W. Haddad, Srilatha Manne. 734-739 [doi]
• Post-Layout Optimization for Deep Submicron DesignKoichi Sato, Masamichi Kawarabayashi, Hideyuki Emura, Naotaka Maeda. 740-745 [doi]
• Enhanced Network Flow Algorithm for Yield OptimizationCyrus Bamji, Enrico Malavasi. 746-751 [doi]
• Hierarchical Electromigration Reliability Diagnosis for VLSI InterconnectsChin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang. 752-757 [doi]
• Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance ExtractionArjan J. van Genderen, N. P. van der Meijs. 758-763 [doi]
• Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal FrequencyP. J. H. Elias, N. P. van der Meijs. 764-769 [doi]
• VDHL Development System and Coding StandardHans Sahm, Claus Mayer, Jörg Pleickhardt, Johannes Schuck, Stefan Späth. 777-782 [doi]
• An Exact Algorithm for Low Power Library-Specific Gate Re-SizingDe-Sheng Chen, Majid Sarrafzadeh. 783-788 [doi]
• Reducing Power Dissipation after Technology Mapping by Structural TransformationsBernhard Rohfleisch, Alfred Kölbl, Bernd Wurth. 789-794 [doi]
• Desensitization for Power Reduction in Sequential CircuitsXiangfeng Chen, Peichen Pan, C. L. Liu. 795-800 [doi]
• Serial Fault EmulationLuc Burgun, Frédéric Reblewski, Gérard Fenelon, Jean Barbier, Olivier Lepape. 801-806 [doi]
• Partial Scan Design Based on Circuit State InformationDong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel. 807-812 [doi]
• Pseudorandom-Pattern Test Resistance in High-Performance DSP DatapathsLaurence Goodby, Alex Orailoglu. 813-818 [doi]
• Hot-Carrier Reliability Enhancement via Input Reordering and Transistor SizingAurobindo Dasgupta, Ramesh Karri. 819-824 [doi]
• A Methodology for Concurrent Fabrication Process/Cell Library OptimizationArun N. Lokanathan, Jay B. Brockman, John E. Renaud. 825-830 [doi]
• Computing Parametric Yield Adaptively Using Local Linear ModelsMien Li, Linda S. Milor. 831-836 [doi]