| 6 | -- | 7 | Allen Dewey. Guest Editor s Introduction: VHDL and Next-Generation Design Automation |
| 8 | -- | 17 | Allen Dewey, Aart J. de Geus. VHDL: Toward a Unified View of Design |
| 18 | -- | 32 | Jayanta Roy, Nand Kumar, Rajiv Dutta, Ranga Vemuri. DSS: A Distributed High-Level Synthesis System |
| 33 | -- | 41 | Vijay Pitchumani, Pankaj Mayor, Nimish Radia. A VHDL Fault Diagnosis Tool Using Functional Fault Models |
| 42 | -- | 56 | Dominique Borrione, Laurence V. Pierre, Ashraf M. Salem. Formal Verification of VHDL Descriptions in the Prevail Environment |
| 58 | -- | 68 | Vijay Nagasamy, Neerav Berry, Carlos Dangelo. Specification, Planning, and Synthesis in a VHDL Design Environment |
| 69 | -- | 81 | Yaohan Chu, Donald L. Dietmeyer, James R. Duley, Fredrick J. Hill, Mario Barbacci, Charles W. Rose, Greg Ordy, Bill Johnson, Martin Roberts. Three Decades of HDLs: Part I, CDL Through TI-HDL |
| 82 | -- | 85 | Colin Maunder. A D&T Special Report-Boundary Scan: An End-of-Term Report-IEEE Std 1149.1 Survey Results |
| 91 | -- | 93 | . DATC Newsletter |
| 94 | -- | 95 | . TTTC Newsletter |